ISPLSI 1032E-70LTI LATTICE SEMICONDUCTOR, ISPLSI 1032E-70LTI Datasheet - Page 11

• Manufacturer Part Number: ISPLSI 1032E-70LTI
• Description: CPLD ispLSI® 1000E Family 6K Gates 128 Macro Cells 70MHz EECMOS Technology 5V 100-Pin TQFP
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPLSI 1032E-70LTI

• Package: 100TQFP
• Family Name: ispLSI® 1000E
• Device System Gates: 6000
• Number Of Macro Cells: 128
• Maximum Propagation Delay Time: 17.5 ns
• Number Of User I/os: 64
• Number Of Logic Blocks/elements: 32
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 70 MHz
• Operating Temperature: -40 to 85 °C

ispLSI 1032E Timing Model
Derivations of
1. Calculations are based upon timing specifications for the ispLSI 1032E-125.
GOE 0,1
Derivations of
Ded. In
I/O Pin
Reset
Y1,2,3
(Input)
Y0
t
t
t
t
t
t
#59
h
co
su
h
co
su
10.9 ns
2.2 ns
3.5 ns
2.9 ns
2.7 ns
5.5 ns
I/O Reg Bypass
D
RST
Register
Input
#28
#22
#23 - 27
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
I/O Cell
t
t
su,
su,
Clock (max) + Reg h - Logic
(
(#22 + #30 + #46) + (#41) - (#22 + #30 + #37)
(0.3 + 2.0 + 4.0) + (4.5) – (0.3 + 2.0 + 5.0)
Clock (max) + Reg co + Output
(
(#22 + #30 + #46) + (#42) + (#47 + #49)
(0.3 + 2.0 + 4.0) + (2.3) + (1.0 + 1.3)
Logic + Reg su - Clock (min)
(
(#22 + #30 + #37) + (#40) – (#54 + #42 + #56)
(0.3 + 2.0 + 5.0) + (0.1) – (1.4 + 2.3 + 0.8)
Clock (max) + Reg h - Logic
(
(#54 + #42 + #56) + (#41) – (#22 + #30 + #37)
(1.4 + 2.3 + 1.8) + (4.5) – (0.3 + 2.0 + 5.0)
Clock (max) + Reg co + Output
(
(#54 + #42 + #56) + (#42) + (#47 + #49)
(1.4 + 2.3 + 1.8) + (2.3) + (1.0 + 1.3)
Logic + Reg su - Clock (min)
(
(#22 + #30 + #37) + (#40) – (#22 + #30 + #46)
(0.3 + 2.0 + 5.0) + (0.1) – (0.3 + 2.0 + 2.9)
t
t
t
t
t
t
iobp +
iobp +
iobp +
gy0(max) +
gy0(max) +
Q
iobp +
t
t
h and
h and
t
t
t
t
grp4 +
grp4 +
grp4 +
grp4 +
t
t
co from the Clock GLB
co from the Product Term Clock
t
t
gco +
gco +
GRP Loading
#29, 31 - 33
Distribution
t
t
t
t
#55 - 58
ptck(max)) + (
20ptxor) + (
20ptxor) + (
Delay
ptck(max)) + (
GRP4
Clock
#30
GRP
#54
#53
t
t
gcp(max)) + (
gcp(max)) + (
t
t
gsu) – (
gsu) – (
t
t
gh) – (
gco) + (
Reg 4 PT Bypass
t
t
XOR Delays
#44 - 46
Control
PTs
gh) – (
gco) + (
Feedback
#36 - 38
t
20 PT
t
gy0(min) +
#35
#59
iobp +
t
iobp +
#34
t
11
1
orp +
OE
t
RE
CK
iobp +
t
orp +
t
Comb 4 PT Bypass
grp4 +
t
grp4 +
t
GLB
Specifications ispLSI 1032E
ob)
t
t
t
gco +
grp4 +
ob)
1
GLB Reg Bypass
D
RST
t
ptck(min))
t
GLB Reg
Table 2-0042a/1032E
20ptxor)
Delay
t
#39
#40 - 43
gcp(min))
t
20ptxor)
Q
ORP Bypass
Delay
ORP
ORP
#48
#47
#49, 50
0491
#51, 52
I/O Cell
(Output)
I/O Pin