ISPLSI 1032E-70LTI LATTICE SEMICONDUCTOR, ISPLSI 1032E-70LTI Datasheet - Page 2

• Manufacturer Part Number: ISPLSI 1032E-70LTI
• Description: CPLD ispLSI® 1000E Family 6K Gates 128 Macro Cells 70MHz EECMOS Technology 5V 100-Pin TQFP
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPLSI 1032E-70LTI

• Package: 100TQFP
• Family Name: ispLSI® 1000E
• Device System Gates: 6000
• Number Of Macro Cells: 128
• Maximum Propagation Delay Time: 17.5 ns
• Number Of User I/os: 64
• Number Of Logic Blocks/elements: 32
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 70 MHz
• Operating Temperature: -40 to 85 °C

Figure 1. ispLSI 1032E Functional Block Diagram
The device also has 64 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered in-
put,
I/O pin with 3-state control. The signal levels are TTL
compatible voltages and the output drivers can source 4
mA or sink 8 mA. Each output can be programmed
independently for fast or slow output slew rate to mini-
mize overall output switching noise.
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 16 universal I/O cells by the ORP. Each ispLSI
1032E device contains four Megablocks.
Functional Block Diagram
latched
MODE/IN 1
input,
SDI/IN 0
RESET
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
ispEN
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
Megablock
output
Logic Blocks
Generic
(GLBs)
A1
A2
A3
A4
A5
A6
A7
A0
or
B0
bi-directional
D7
B1
D6
Output Routing Pool (ORP)
B2
Output Routing Pool (ORP)
D5
B3
Input Bus
Routing
Global
(GRP)
Pool
D4
Input Bus
B4
2
The GRP has, as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 1032E device are selected using the
Clock Distribution Network. Four dedicated clock pins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
also be driven from a special clock GLB (C0 on the ispLSI
1032E device). The logic of this GLB allows the user to
create an internal clock from a combination of internal
signals within the device.
D3
B5
Specifications ispLSI 1032E
D2
B6
D1
B7
D0
Distribution
Network
C6
C5
C4
C3
C2
C1
C0
C7
Clock
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
GOE 1/IN 5
GOE 0/IN 4
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32