ISPLSI 5256VE-80LT100I LATTICE SEMICONDUCTOR, ISPLSI 5256VE-80LT100I Datasheet - Page 15

• Manufacturer Part Number: ISPLSI 5256VE-80LT100I
• Description: CPLD ispLSI® 5000VE Family 12K Gates 256 Macro Cells 80MHz EECMOS Technology 3.3V 100-Pin TQFP
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPLSI 5256VE-80LT100I

• Package: 100TQFP
• Family Name: ispLSI® 5000VE
• Device System Gates: 12000
• Number Of Macro Cells: 256
• Maximum Propagation Delay Time: 15 ns
• Number Of User I/os: 72
• Number Of Logic Blocks/elements: 8
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 80 MHz
• Number Of Product Terms Per Macro: 35
• Operating Temperature: -40 to 85 °C

Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet
for further details.
Internal Timing Parameters
PARAMETER
In/Out Delays
t
t
t
t
t
t
t
Routing/GLB Delays
t
t
t
t
t
t
Register/Latch Delays
t
t
t
t
t
t
t
t
t
t
t
t
Control Delays
t
t
t
t
t
t
in
gclk_in
rst
goe
buf
en
dis
route
pdb
pdi
ptsa
fbk
inreg
s
s_pt
h
coi
sl
hl
goi
pdli
ces
ceh
sri
srr
ptclk
bclk
ptsr
bsr
ptoe
gptoe
Input Buffer Delay
Global Clock Buffer Input Delay (clk0)
Global Reset Pin Delay
Global OE Pin Delay
Output Buffer Delay
Output Enable Delay
Output Disable Delay
GRP and Logic Delay
5-pt Bypass Propagation Delay
Combinatorial Propagation Delay
Product Term Sharing Array
Internal Feedback Delay
Input Buffer to Macrocell Register Delay
Register Setup Time
Register Setup Time (Product Term Clock)
Register Hold Time
Register Clock to GLB Output Delay
Latch Setup Time
Latch Hold Time
Latch Gate to GLB Output Delay
GLB Latch propagation Delay
Clock Enable Setup Time
Clock Enable Hold Time
Asynchronous Set/Reset to GLB Output Delay
Asynchronous Set/Reset Recovery Time
Macrocell PT Clock Delay
Block PT Clock Delay
Macrocell PT Set/Reset Delay
Block PT Set/Reset Delay
Macrocell PT OE Delay
Global PT OE Delay
DESCRIPTION
Over Recommended Operating Conditions
15
Specifications ispLSI 5256VE
MIN MAX MIN MAX MIN
0.6
0.6
2.4
0.6
2.4
4.1
0.9
0.8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
-165
0.6
0.7
4.9
3.2
1.9
1.3
1.3
3.2
0.3
0.0
1.8
0.0
2.0
0.4
0.4
1.0
1.2
0.4
1.4
2.1
3.1
1.9
6.9
–
–
–
–
–
–
–
–
1.0
1.0
3.0
1.0
3.0
4.3
1.7
1.2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
-125
1.3
1.3
6.6
3.9
2.2
1.6
1.6
3.6
0.4
0.0
2.4
0.0
2.5
1.0
1.0
1.5
1.2
0.4
1.9
3.7
5.7
2.0
7.5
–
–
–
–
–
–
–
–
1.5
1.5
4.0
1.5
4.0
5.3
2.7
1.2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
-100
MAX MIN MAX UNIT
2.3
1.8
7.1
5.9
2.7
1.6
1.6
4.0
1.0
0.0
3.0
0.0
2.5
1.5
1.5
2.0
1.7
0.5
2.5
4.8
6.8
2.1
7.6
–
–
–
–
–
–
–
–
1.5
1.5
5.0
1.5
5.0
6.3
3.7
2.2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
-80
2.3
1.8
7.1
7.4
3.7
1.6
1.6
4.5
1.5
0.0
4.5
0.5
3.5
1.5
1.5
2.5
2.2
0.5
2.5
4.8
6.8
3.6
8.6
–
–
–
–
–
–
–
–
Timing v.2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns