ISPLSI 5256VE-80LT100I LATTICE SEMICONDUCTOR, ISPLSI 5256VE-80LT100I Datasheet - Page 2

• Manufacturer Part Number: ISPLSI 5256VE-80LT100I
• Description: CPLD ispLSI® 5000VE Family 12K Gates 256 Macro Cells 80MHz EECMOS Technology 3.3V 100-Pin TQFP
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPLSI 5256VE-80LT100I

• Package: 100TQFP
• Family Name: ispLSI® 5000VE
• Device System Gates: 12000
• Number Of Macro Cells: 256
• Maximum Propagation Delay Time: 15 ns
• Number Of User I/os: 72
• Number Of Logic Blocks/elements: 8
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 80 MHz
• Number Of Product Terms Per Macro: 35
• Operating Temperature: -40 to 85 °C

Figure 1. ispLSI 5256VE Functional Block Diagram (144-I/O Option)
Functional Block Diagram
RESET
VCCIO
I/O 14
I/O 15
I/O 16
I/O 17
I/O 32
I/O 33
I/O 34
I/O 35
1 TOE
I/O 18
I/O 19
I/O 20
I/O 21
I/O 1
I/O 2
I/O 3
1. CLK2, CLK3 and TOE signals are shared with I/O signals. Use the table below to determine
which I/O is shared by package type.
Package Type
100 TQFP
128 TQFP
256 fpBGA
272 BGA
Logic Block
Logic Block
Generic
Generic
Input Bus
Input Bus
1/O 44 / CLK2
I/O 59 / CLK2
I/O 119 / CLK2
I/O 119 / CLK2
Global Routing Pool
(GRP)
Multplexed Signals
2
I/O 49 / CLK 3
I/O 65 / CLK3
I/O 131 / CLK3
I/O 131 / CLK3
Specifications ispLSI 5256VE
Logic Block
Logic Block
Generic
Generic
Input Bus
Input Bus
I/O 0 / TOE
I/O 0 / TOE
I/O 0 / TOE
I/O 0 / TOE
Boundary
Interface
Scan
TDI
TDO
I/O 93
I/O 92
I/O 91
I/O 90
I/O 107
I/O 106
I/O 105
I/O 104
I/O 75
I/O 74
I/O 73
I/O 72
I/O 89
I/O 88
I/O 87
I/O 86