XC2C32A-6CPG56C Xilinx Inc, XC2C32A-6CPG56C Datasheet - Page 13

• Manufacturer Part Number: XC2C32A-6CPG56C
• Description: CPLD CoolRunner™-II Family 750 Gates 32 Macro Cells 200MHz 0.18um (CMOS) Technology 1.8V 56-Pin CSBGA
• Manufacturer: Xilinx Inc
• Series: CoolRunner IIr

Specifications of XC2C32A-6CPG56C

• Package: 56CSBGA
• Family Name: CoolRunner™-II
• Device System Gates: 750
• Number Of Macro Cells: 32
• Maximum Propagation Delay Time: 6 ns
• Number Of User I/os: 33
• Number Of Logic Blocks/elements: 2
• Typical Operating Supply Voltage: 1.8 V
• Maximum Operating Frequency: 200 MHz
• Number Of Product Terms Per Macro: 40
• Operating Temperature: 0 to 70 °C
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 5.5ns
• Voltage Supply - Internal: 1.7 V ~ 1.9 V
• Number Of Logic Elements/blocks: 2
• Number Of Macrocells: 32
• Number Of Gates: 750
• Number Of I /o: 33
• Mounting Type: Surface Mount
• Package / Case: 56-CSBGA
• Features: Programmable
• Voltage: 1.8V
• Memory Type: CMOS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1403

Additional Information
Additional information is available for the following CoolRunner-II topics:
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Revision History
The following table shows the revision history for this document.
DS310 (v2.1) November 6, 2008
Product Specification
10/01/04
11/08/04
11/22/04
02/17/05
03/07/05
06/28/05
03/20/06
02/15/07
03/08/07
11/06/08
6/15/04
8/30/04
XAPP784: Bulletproof CPLD Design Practices
XAPP375: Timing Model
XAPP376: Logic Engine
XAPP378: Advanced Features
XAPP382: I/O Characteristics
XAPP389: Powering CoolRunner-II
XAPP399: Assigning VREF Pins
Date
R
Version
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
Initial Xilinx release.
Pb-free documentation
Add Asynchronous Preset/Reset Pulse Width specification to AC Electrical Characteristics.
Product Release. No changes to documentation.
Changes to output enable/disable specifications; changes to I
Changes to f
Improvement of pin-to-pin logic delay, page 1. Modifications to Table 1, IOSTANDARDs.
Move to Product Specification. Change to T
Add Warranty Disclaimer. Add note to Pin Descriptions that
be used for general purpose I/O.
Change to V
grade.
Fixed typo in note for V
Added note to Pin Description tables to indicate the PC44 packages are obsolete. Removed
part numbers for devices in PC44 packages from ordering information. See Product
Discontinuation Notice
IH
TOGGLE
specification for 2.5V and 1.8V LVCMOS. Change to T
, t
SLEW25
www.xilinx.com
IL
xcn07022.pdf
for LVCMOS18; removed note for V
, and t
To access these and all application notes with their associ-
ated reference designs, click the following links and scroll
down the page until you find the document you want:
CoolRunner-II CPLD Data Sheets and Application Notes
Device Packages
SLEW33
.
Revision
IN25
, T
OUT25
, T
IN33
GCK, GSR, and GTS pins can also
XC2C32A CoolRunner-II CPLD
IL
CCSB
, and T
for LVCMOS33.
.
OEM
OUT33
for -4 speed
.
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