XC2C32A-6CPG56C Xilinx Inc, XC2C32A-6CPG56C Datasheet - Page 3

CPLD CoolRunner™-II Family 750 Gates 32 Macro Cells 200MHz 0.18um (CMOS) Technology 1.8V 56-Pin CSBGA

XC2C32A-6CPG56C

Manufacturer Part Number
XC2C32A-6CPG56C
Description
CPLD CoolRunner™-II Family 750 Gates 32 Macro Cells 200MHz 0.18um (CMOS) Technology 1.8V 56-Pin CSBGA
Manufacturer
Xilinx Inc
Series
CoolRunner IIr
Datasheets

Specifications of XC2C32A-6CPG56C

Package
56CSBGA
Family Name
CoolRunner™-II
Device System Gates
750
Number Of Macro Cells
32
Maximum Propagation Delay Time
6 ns
Number Of User I/os
33
Number Of Logic Blocks/elements
2
Typical Operating Supply Voltage
1.8 V
Maximum Operating Frequency
200 MHz
Number Of Product Terms Per Macro
40
Operating Temperature
0 to 70 °C
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
5.5ns
Voltage Supply - Internal
1.7 V ~ 1.9 V
Number Of Logic Elements/blocks
2
Number Of Macrocells
32
Number Of Gates
750
Number Of I /o
33
Mounting Type
Surface Mount
Package / Case
56-CSBGA
Features
Programmable
Voltage
1.8V
Memory Type
CMOS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1403

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Absolute Maximum Ratings
Recommended Operating Conditions
DC Electrical Characteristics Over Recommended Operating Conditions
DS310 (v2.1) November 6, 2008
Product Specification
Notes:
1.
2.
3.
Notes:
1.
2.
I
I
I
C
C
C
I
I
CCSB
CCSB
CC
IL
IH
Symbol
JTAG
CLK
IO
(2)
(2)
Symbol
V
(1)
Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions,
the device pins might undershoot to –2.0V or overshoot to +4.5V, provided this overshoot or undershoot lasts less than 10 ns and
with the forcing current being limited to 200 mA.
Valid over commercial temperature range.
For soldering guidelines and thermal considerations, see the
packages, see XAPP427.
16-bit up/down resettable binary counter (one per Function Block) tested at
See Quality and Reliability section of the CoolRunner-II family data sheet.
Symbol
V
V
V
T
CCAUX
V
V
V
V
JTAG
CCIO
CCAUX
STG
V
CC
CCIO
TS
IN
T
CC
J
(1)
(1)
(3)
(2)
R
Standby current Commercial
Standby current Industrial
Dynamic current
JTAG input capacitance
Global clock input capacitance
I/O capacitance
Input leakage current
I/O High-Z leakage
Supply voltage for internal logic
and input buffers
Supply voltage for output drivers @ 3.3V operation
Supply voltage for output drivers @ 2.5V operation
Supply voltage for output drivers @ 1.8V operation
Supply voltage for output drivers @ 1.5V operation
JTAG programming pins
Supply voltage relative to ground
Supply voltage for output drivers
JTAG input voltage limits
JTAG input supply voltage
Input voltage relative to ground
Voltage applied to 3-state output
Storage Temperature (ambient)
Junction Temperature
Parameter
Description
Parameter
V
V
V
V
CC
CC
IN
IN
= 0V or V
= 0V or V
= 1.9V, V
= 1.9V, V
www.xilinx.com
Commercial T
Industrial T
Test Conditions
f = 50 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
Device Packaging
CCIO
CCIO
CCIO
CCIO
A
to 3.9V
to 3.9V
= 3.6V
= 3.6V
= –40°C to +85°C
A
= 0°C to +70°C
V
CC
information on the Xilinx website. For Pb free
= V
CCIO
Typical
= 1.9V.
22
38
-
-
-
-
-
-
-
XC2C32A CoolRunner-II CPLD
–65 to +150
Min
–0.5 to 2.0
–0.5 to 4.0
–0.5 to 4.0
–0.5 to 4.0
–0.5 to 4.0
–0.5 to 4.0
1.7
1.7
3.0
2.3
1.7
1.4
1.7
Value
+150
Max.
0.25
150
+/-1
+/-1
2.5
90
10
12
10
Max
1.9
1.9
3.6
2.7
1.9
1.6
3.6
Units
Units
Units
mA
mA
μA
μA
μA
μA
pF
pF
pF
°C
°C
V
V
V
V
V
V
V
V
V
V
V
V
V
3

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