XC2C32A-6CPG56C Xilinx Inc, XC2C32A-6CPG56C Datasheet - Page 5

• Manufacturer Part Number: XC2C32A-6CPG56C
• Description: CPLD CoolRunner™-II Family 750 Gates 32 Macro Cells 200MHz 0.18um (CMOS) Technology 1.8V 56-Pin CSBGA
• Manufacturer: Xilinx Inc
• Series: CoolRunner IIr

Specifications of XC2C32A-6CPG56C

• Package: 56CSBGA
• Family Name: CoolRunner™-II
• Device System Gates: 750
• Number Of Macro Cells: 32
• Maximum Propagation Delay Time: 6 ns
• Number Of User I/os: 33
• Number Of Logic Blocks/elements: 2
• Typical Operating Supply Voltage: 1.8 V
• Maximum Operating Frequency: 200 MHz
• Number Of Product Terms Per Macro: 40
• Operating Temperature: 0 to 70 °C
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 5.5ns
• Voltage Supply - Internal: 1.7 V ~ 1.9 V
• Number Of Logic Elements/blocks: 2
• Number Of Macrocells: 32
• Number Of Gates: 750
• Number Of I /o: 33
• Mounting Type: Surface Mount
• Package / Case: 56-CSBGA
• Features: Programmable
• Voltage: 1.8V
• Memory Type: CMOS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1403

Schmitt Trigger Input DC Voltage Specifications
AC Electrical Characteristics Over Recommended Operating Conditions
DS310 (v2.1) November 6, 2008
Product Specification
Notes:
1.
2.
3.
4.
V
V
V
T
T
T
T
T
T
T
T
F
F
F
F
F
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Symbol
AO
APRPW
OE
PD1
PD2
SUD
SU1
SU2
HD
H
CO
TOGGLE
SYSTEM1
SYSTEM2
EXT1
EXT2
PSUD
PSU1
PSU2
PHD
PH
PCO
POE
MOE
PAO
SUEC
HEC
CW
PCW
CONFIG
CCIO
T+
T-
Symbol
F
F
macrocell while F
F
Typical configuration current during T
/T
TOGGLE
SYSTEM1
EXT1
/T
/T
(3)
(3)
OD
POD
MOD
(4)
(1)
(1/T
(2)
(2)
R
is the maximum clock frequency to which a T-Flip Flop can reliably toggle (see the CoolRunner-II family data sheet).
Input source voltage
Input hysteresis threshold voltage
(1/T
SU1
+T
Propagation delay single p-term
Propagation delay OR array
Direct input register clock setup time
Setup time fast (single p-term)
Setup time (OR array)
Direct input register hold time
P-term hold time
Clock to output
Internal toggle rate
Maximum system frequency
Maximum system frequency
Maximum external frequency
Maximum external frequency
Direct input register p-term clock setup time
P-term clock setup time (single p-term)
P-term clock setup time (OR array)
Direct input register p-term clock hold time
P-term clock hold
P-term clock to output
Global OE to output enable/disable
P-term OE to output enable/disable
Macrocell driven OE to output enable/disable
P-term set/reset to output valid
Global set/reset to output valid
Register clock enable setup time
Register clock enable hold time
Global clock pulse width High or Low
P-term pulse width High or Low
Asynchronous preset/reset pulse width (High or Low)
Configuration time
CYCLE
CO
SYSTEM2
) is the maximum external frequency using one p-term while F
) is the internal operating frequency for a device fully populated with one 16-bit counter through one p-term per
Parameter
is through the
CONFIG
OR array
Parameter
is 500
.
μ
A.
www.xilinx.com
Test Conditions
EXT2
is through the
Min.
1.7
1.9
2.1
0.0
0.0
0.4
0.6
0.8
1.5
1.3
2.0
0.0
1.4
4.0
4.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.5 x V
0.2 x V
Min.
-4
1.4
XC2C32A CoolRunner-II CPLD
Max.
500
323
303
179
172
CCIO
CCIO
3.8
4.0
3.7
5.0
4.7
6.2
6.2
5.5
4.5
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
OR array
Min.
0.8 x V
0.5 x V
2.2
2.6
3.1
0.0
0.0
0.9
1.3
1.8
1.6
1.2
3.0
0.0
2.2
6.0
6.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max.
.
3.9
-6
CCIO
CCIO
Max.
300
200
182
137
128
5.5
6.0
4.7
6.0
5.5
6.7
6.9
6.8
5.5
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Units
Units
MHz
MHz
MHz
MHz
MHz
V
V
V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
5