XC3S700AN-4FG484I Xilinx Inc, XC3S700AN-4FG484I Datasheet - Page 92

• Manufacturer Part Number: XC3S700AN-4FG484I
• Description: FPGA Spartan®-3AN Family 700K Gates 13248 Cells 667MHz 90nm Technology 1.2V 484-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S700AN-4FG484I

• Package: 484FBGA
• Family Name: Spartan®-3AN
• Device Logic Units: 13248
• Device System Gates: 700000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 372
• Ram Bits: 368640
• Number Of Logic Elements/cells: 13248
• Number Of Labs/clbs: 1472
• Total Ram Bits: 368640
• Number Of I /o: 372
• Number Of Gates: 700000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

FGG400: 400-Ball Fine-Pitch Ball Grid Array
The 400-ball fine-pitch ball grid array, FGG400, supports the XC3S400AN FPGA as shown in
Table 76
differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type (as
defined in
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at:
www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip.
Pinout Table
Table 76: Spartan-3AN FGG400 Pinout
DS557 (v4.1) April 1, 2011
Product Specification
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
lists all the FGG400 package pins. They are sorted by bank number and then by pin name. Pins that form a
Table
IO_L01N_0
IO_L01P_0
IO_L02N_0
IO_L02P_0/VREF_0
IO_L03N_0
IO_L03P_0
IO_L04N_0
IO_L04P_0/VREF_0
IO_L05N_0
IO_L05P_0
IO_L06N_0
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
IO_L09N_0
IO_L09P_0
IO_L10N_0/VREF_0
IO_L10P_0
IO_L11N_0
IO_L11P_0
IO_L12N_0
IO_L12P_0
IO_L13N_0
IO_L13P_0
IO_L14N_0
IO_L14P_0
IO_L15N_0/GCLK5
IO_L15P_0/GCLK4
IO_L16N_0/GCLK7
62).
Pin Name
FGG400
Ball
C17
D17
D16
C16
C15
D15
C14
C13
D14
C12
D12
C11
D11
C10
A18
B18
E15
A17
B17
A16
A14
A15
B15
F13
E13
B13
F12
A12
B12
B11
E11
VREF
VREF
VREF
GCLK
GCLK
GCLK
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
www.xilinx.com
Table 76: Spartan-3AN FGG400 Pinout (Cont’d)
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Spartan-3AN FPGA Family: Pinout Descriptions
IO_L16P_0/GCLK6
IO_L17N_0/GCLK9
IO_L17P_0/GCLK8
IO_L18N_0/GCLK11
IO_L18P_0/GCLK10
IO_L19N_0
IO_L19P_0
IO_L20N_0
IO_L20P_0
IO_L21N_0
IO_L21P_0
IO_L22N_0/VREF_0
IO_L22P_0
IO_L23N_0
IO_L23P_0
IO_L24N_0
IO_L24P_0
IO_L25N_0
IO_L25P_0
IO_L26N_0
IO_L26P_0
IO_L27N_0
IO_L27P_0
IO_L28N_0
IO_L28P_0
IO_L29N_0
IO_L29P_0
IO_L30N_0
IO_L30P_0
IO_L31N_0
IO_L31P_0
Pin Name
Table 76
FGG400
and
Ball
A10
E10
D10
A8
A9
C9
B9
C8
B8
D8
C7
F9
E9
E8
A7
B7
C6
A6
B5
A5
E7
D6
C5
C4
A4
B3
A3
E6
F8
F7
F6
Figure
GCLK
GCLK
GCLK
GCLK
GCLK
VREF
Type
22.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
92