MAX3542CLM+T Maxim Integrated Products, MAX3542CLM+T Datasheet - Page 10

• Manufacturer Part Number: MAX3542CLM+T
• Description: RF Receiver Single-conversion Te levision tuner Integ
• Manufacturer: Maxim Integrated Products

Specifications of MAX3542CLM+T

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Complete Single-Conversion
Television Tuner
The MAX3542 includes 11 programmable registers and
two read-only registers. The 11 programmable registers
include two N-divider registers, an R-divider register, a
VCO register, an IFOVLD/Charge Pump/Filter Select
register, a Control register, a Shutdown register, and
Table 1. Register Configuration
Table 2. N-DIV High Register (Address: 0000 b )
10
S er i es C ap aci tor
and Fi l ter S el ect
P ar al lel Cap acitor
Data Readback
RESERVED
C har g e P um p ,
Tracking Filter
ROM Address
BIT NAME
Tr acki ng Fi l ter
Tracking Fi l ter
REGISTER
N-DIV High
ROM Table
N-DIV Low
N[14:8]
Shutdown
Reserved
IFO V LD ,
Control
NAME
______________________________________________________________________________________
Status
R-DIV
VCO
BIT LOCATION (0 = LSB)
WRITE
READ/
Read
Read
Both
Both
Both
Both
Both
Both
Both
Both
Both
Both
Both
Detailed Description
6–0
REGISTER
ADDRESS
7
0x0C
0x0A
0x0B
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
Register Descriptions
MSB
SHDN
_MIX1
VCO4
TFR7
TFS7
POR
RECOMMENDED
FLD
D7
N7
X
0
0
0
0
0
DEFAULT
0000001
0
IFOVLD2
SHDN
_MIX0
VCO3
TFR6
TFS6
N14
LD2
D6
N6
R6
0
0
0
X
Must be set to 0.
Sets the most significant bits of the PLL integer divider (N). Default
integer divider value is N = 4688. N can range from 256 to 32,767.
IFOVLD1
SHDN
VCO2
TFR5
TFS5
TFP5
N13
LD1
_IF
D5
N5
R5
X
0
0
Tracking Filter Control registers. These 11 programma-
ble registers are also readable. The read-only registers
include a Status register and a ROM Table Data register.
Recommended default bit settings are provided for
user convenience only and are not guaranteed. The
user must write all registers after power-up and no earli-
er than 100μs after power-up.
IFOVLD0
SHDN
VCO1
TFR4
TFS4
TFP4
N12
_OD
LD0
D4
N4
R4
X
DATA BYTE
0
0
VCO0
SHDN
SHDN
_SYN
TFA3
TFR3
TFS3
TFP3
CP1
N11
_RF
D3
N3
R3
X
X
FUNCTION
_IFVGA
SHDN
TFS2
TFP2
TFA2
TFR2
N10
CP0
D2
N2
LD
R2
0
X
X
VDIV1
INPT1
TFS1
TFP1
TFA1
TFR1
TF1
D1
N9
N1
R1
0
X
X
VDIV0
INPT0
TFA0
TFR0
TFS0
TFP0
TF0
D0
N8
N0
R0
0
X
X
LSB