MAX3542CLM+T Maxim Integrated Products, MAX3542CLM+T Datasheet - Page 15

• Manufacturer Part Number: MAX3542CLM+T
• Description: RF Receiver Single-conversion Te levision tuner Integ
• Manufacturer: Maxim Integrated Products

Specifications of MAX3542CLM+T

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

When addressed with a write command, the MAX3542
allows the master to write to a single register or to multi-
ple successive registers.
A write cycle begins with the bus master issuing a
START condition followed by the seven slave address
bits and a write bit (R/W = 0). The MAX3542 issues an
ACK if the slave address byte is successfully received.
The bus master must then send to the slave the
address of the first register it wishes to write to. If the
slave acknowledges the address, the master can then
write one byte to the register at the specified address.
Data is written beginning with the most significant bit.
The MAX3542 again issues an ACK if the data is suc-
cessfully written to the register. The master can contin-
ue to write data to the successive internal registers with
the MAX3542 acknowledging each successful transfer,
or it can terminate transmission by issuing a STOP con-
dition. The write cycle does not terminate until the mas-
ter issues a STOP condition.
Figure 2 illustrates an example in which registers 0
through 2 are written with 0x0E, 0xD8, and 0xE1,
respectively.
Figure 2. Example: Write Registers 0 through 2 with 0x0E, 0xD8, and 0xE1, Respectively
Figure 3. Example: Read Data from Registers 0 and 1
START
START
11000[ADDR2][ADDR1]
11000[ADDR2][ADDR1]
WRITE DEVICE
WRITE DEVICE
ADDRESS
ADDRESS
______________________________________________________________________________________
R/W
R/W
0
0
ACK
—
ACK
—
WRITE 1ST REGISTER
WRITE REGISTER
ADDRESS
ADDRESS
0x00
0x00
Write Cycle
Complete Single-Conversion
ACK
—
ACK
—
START
WRITE DATA TO
REGISTER 0x00
11000[ADDR2][ADDR1]
0x0E
WRITE DEVICE
A read cycle begins with the bus master issuing a
START condition followed by the seven slave address
bits and a write bit (R/W = 0). The MAX3542 issues an
ACK if the slave address byte is successfully
received. The master then sends the 8-bit address of
the first register that it wishes to read. The MAX3542
then issues another ACK. Next, the master must issue
a START condition followed by the seven slave
address bits and a read bit (R/W = 1). The MAX3542
issues an ACK if it successfully recognizes its address
and begins sending data from the specified register
address starting with the most significant bit (MSB).
Data is clocked out of the MAX3542 on the rising edge
of SCL. On the 9th rising edge of SCL, the master can
issue an ACK and continue reading successive regis-
ters or it can issue a NACK followed by a STOP condi-
tion to terminate transmission. The read cycle does
not terminate until the master issues a STOP condi-
tion. Figure 3 illustrates an example in which registers
0 and 1 are read back.
ADDRESS
ACK
—
WRITE DATA TO
R/W
REGISTER 0x01
1
0xD8
Television Tuner
ACK
—
READ DATA
D7–D0
REG 0
ACK
—
ACK
—
WRITE DATA TO
REGISTER 0x02
READ DATA
0xE1
D7–D0
REG 1
NACK
ACK
—
—
Read Cycle
STOP
STOP
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