MAX3542CLM+T Maxim Integrated Products, MAX3542CLM+T Datasheet - Page 16

• Manufacturer Part Number: MAX3542CLM+T
• Description: RF Receiver Single-conversion Te levision tuner Integ
• Manufacturer: Maxim Integrated Products

Specifications of MAX3542CLM+T

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Complete Single-Conversion
Television Tuner
The MAX3542 features separate UHF and VHF inputs
that are matched to 75Ω. Both inputs require a DC-
blocking capacitor. The active inputs are selected by
the input registers. In addition, the input registers
enable or disable the lowpass filter, which can be used
when the VHF input is selected. For 47MHz to 100MHz,
select the VHF_IN with the LPF filter enabled (INPT =
00). For 100MHz to 326MHz, select VHF_IN with LPF
disabled (INPT = 01). For 326MHz to 862MHz, select
UHF_IN (INPT = 10).
The separate VHF and UHF inputs can be driven from a
single RF source using a diplex filter. For diplex filter
schematic and component values, refer to the
MAX3542 Evaluation Kit data sheet.
The gain of the RF LNA can be adjusted over a typical
range of 45dB with the RFAGC pin. The RFAGC input
accepts a DC voltage from 0.5V to 3V, with 3V provid-
ing maximum gain. This pin can be controlled with the
IF power-detector output to form a closed RF gain-con-
trol loop. See the Closed-Loop RF Gain Control section
for more information.
The MAX3542 includes a programmable tracking filter
for each band of operation to optimize rejection of
out-of-band interference while minimizing insertion
Table 16. ROM Table
16
DESCRIPTION ADDRESS
Reserved
VHF High
VHF High
VHF High
VHF Low
VHF Low
VHF Low
______________________________________________________________________________________
UHF
UHF
UHF
Applications Information
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
MSB
HS0[1]
HP0[3]
US0[5]
US1[3]
UP0[1]
LS0[5]
LS1[1]
LP1[3]
OD[2]
D7
RF Tracking Filter
RF Gain Control
HS0[0]
HP0[2]
US0[4]
US1[2]
UP0[0]
LS0[4]
LS1[0]
LP1[2]
OD[1]
D6
RF Inputs
HS1[3]
HP0[1]
US0[3]
US1[1]
UP1[5]
LS0[3]
LP0[5]
LP1[1]
OD[0]
D5
loss for the desired received signal. The center fre-
quency of each tracking filter is selected by a
switched-capacitor array that is programmed by the
TFS[7:0] bits in the Tracking Filter Series Capacitor
register and the TFP[5:0] bits in the Tracking Filter
Parallel Capacitor register.
Optimal tracking filter settings for each channel vary
from part to part due to process variations. To accom-
modate part-to-part variations, each part is factory cali-
brated by Maxim. During calibration, the y-intercept
and slope for the series and parallel tracking capacitor
arrays are calculated and written into an internal ROM
table. The user must read the ROM table upon power-
up and store the data in local memory (8 bytes total) to
calculate the optimal TFS[7:0] and TFP[5:0] settings for
each channel. Table 16 shows the address and bits for
each ROM table entry. See the Interpolating Tracking
Filter Coefficients section for more information on how
to calculate the required values.
Each ROM table entry must be read using a two-step
process. First, the address of the ROM bits to be read
must be programmed into the TFA[3:0] bits in the
Tracking Filter ROM Address register (Table 11).
Once the address has been programmed, the data
stored in that address is transferred to the TFR[7:0] bits
in the ROM Table Data Readback register (Table 13).
The ROM data at the specified address can then be
read from the TFR[7:0] bits and stored in the micro-
processor’s local memory.
HS1[2]
HP0[0]
US0[2]
US1[0]
UP1[4]
LS0[2]
LP0[4]
LP1[0]
D4
X
DATA BYTE
HS0[5]
HS1[1]
HP1[3]
US0[1]
UP0[5]
UP1[3]
LS0[1]
LP0[3]
D3
X
HS0[4]
HS1[0]
HP1[2]
US0[0]
UP0[4]
UP1[2]
LS0[0]
LP0[2]
D2
X
Reading the ROM Table
HS0[3]
HP0[5]
HP1[1]
US1[5]
UP0[3]
UP1[1]
LS1[3]
LP0[1]
D1
X
HS0[2]
HP0[4]
HP1[0]
US1[4]
UP0[2]
UP1[0]
LS1[2]
LP0[0]
D0
X
LSB