MAX3542CLM+T Maxim Integrated Products, MAX3542CLM+T Datasheet - Page 17

• Manufacturer Part Number: MAX3542CLM+T
• Description: RF Receiver Single-conversion Te levision tuner Integ
• Manufacturer: Maxim Integrated Products

Specifications of MAX3542CLM+T

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The TFS[7:0] and TFP[5:0] bits must be reprogrammed
for each channel frequency to optimize performance.
The optimal settings for each channel can be calculat-
ed from the ROM table data using the equations below:
Analog (PAL) Channels:
VHF_LO Filter:
VHF_HI Filter:
:
UHF Filter:
where:
Digital (DVB-T) channels:
Consult the factory for DVB-T coefficients.
The MAX3542 includes a broadband IF overload detec-
tor, which provides an indication of the total power pre-
sent at the RF input. The overload-detector output voltage
is compared to a reference voltage, and the difference is
amplified. This error signal drives an open-collector tran-
sistor whose collector is connected to the IFOVLD pin,
causing the IFOVLD pin to sink current. The nominal full-
scale current sunk by the IFOVLD pin is 300μA. The
IFOVLD pin requires a 10kΩ pullup resistor to V
The IF overload detector is calibrated at the factory to
attack at 0.7V
baseband processor must read OD[2:0] from the ROM
table and store it in the IFOVLD register.
TFS
TFP INT[10
TFS
TFP INT[10
TFS
TFP INT[10
f
TFS = decimal value of the optimal TFS[7:0] setting
TFP = decimal value of the optimal TFP[5:0] setting
LS0, LS1, LP0, LP1, HS0, HS1, HP0, HP1, US0,
US1, UP0, and UP1 = the decimal values of the
ROM table coefficients (Table 16).
RF
=
=
=
=
=
=
INT[
INT[
INT[
= operating frequency in megahertz.
10
10
10
(Table 9) for the given operating frequency.
(Table 10) for the given operating frequency.
[(1.1
[(1.3
[(
[(0.8
[(0.8
[(0.8
Interpolating Tracking Filter Coefficients
US0
64
P-P
×
×
×
×
×
+ 3)
UP0
HS0
LS0
HP
LP
64
______________________________________________________________________________________
64
64
64
64
at the IFOUT1. Upon power-up, the
0 0
0 0
+
+
+ 2.2)
+ 2.5)
+ 1.6)
+ 1.6)
(2
1 1 .6)
×
US1
64
+
+
+
+
+
(2
(4
(1.6
(4
IF Overload Detector
(8
- 3)
×
×
×
×
UP1
×
×
64
HS1
LS1
LP1
16
16
16
f f
HP1
RF
16
- 2.5)
- 8)
- 12)
- 14)
×
- 3.2)
10 ]
×
×
-3
×
×
f
f
RF
RF
×
]
f
f
RF
RF
- 20
f
×
×
RF
×
×
10 ]
CC
10 ]
10 ]
10 ]
×
-3
-3
Complete Single-Conversion
-3
.
-3
10
] - 1
] 10
] 10
- - 3
]
−
−
]
]
0 0
Closed-loop RF gain control can be implemented by
connecting the IFOVLD output to the RFAGC input.
Using a 10kΩ pullup resistor on the IFOVLD pin as
shown in the Typical Application Circuit results in a
nominal control voltage range of 0.5V to 3V.
The MAX3542 frequency synthesizer includes three
VCOs and eight VCO sub-bands to guarantee
a 2200MHz to 4400MHz VCO frequency range. The fre-
quency synthesizer also features an additional VCO
frequency divider that must be programmed to either 4,
8, 16, or 32 by the VDIV[1:0] bits in the VCO register
based on the channel being received.
To ensure PLL lock, the proper VCO and VCO sub-
band for the channel being received must be chosen
by iteratively selecting a VCO and VCO sub-band, then
reading the LD[2:0] bits to determine if the PLL is
locked. Any reading from 001 to 110 indicates the PLL
is locked. If LD[2:0] reads 000, the PLL is unlocked and
the selected VCO is at the bottom of its tuning range; a
lower VCO sub-band must be selected. If LD[2:0] reads
111, the PLL is unlocked and the selected VCO is at the
top of its tuning range; a higher VCO sub-band must be
selected. The VCO and VCO sub-band settings should
be progressively increased or decreased until the
LD[2:0] reading falls in the 001 to 110 range.
Due to overlap between VCO sub-band frequencies,
it is possible that multiple VCO settings can be used
to tune to the same channel frequency. System per-
formance at a given channel should be similar
between the various possible VCO settings, so it is
sufficient to select the first VCO and VCO sub-band
that provides lock.
The MAX3542 EV kit can serve as a guide for PCB lay-
out. Keep RF signal lines as short as possible to mini-
mize losses and radiation. Use controlled impedance on
all high-frequency traces. The exposed paddle must be
soldered evenly to the board’s ground plane for proper
operation. Use abundant vias beneath the exposed pad-
dle for maximum heat dissipation. Use abundant ground
vias between RF traces to minimize undesired coupling.
To minimize coupling between different sections of the
IC, the ideal power-supply layout is a star configuration,
which has a large decoupling capacitor at the central
V
with each trace going to separate V
MAX3542. Each V
with a low impedance to ground at the frequency of
interest. Do not share ground vias among multiple con-
nections to the PCB ground plane.
CC
node. The V
VCO and VCO Divider Selection
Television Tuner
CC
CC
Closed-Loop RF Gain Control
traces branch out from this node,
pin must have a bypass capacitor
Layout Considerations
CC
pins of the
17