TEA5764UK/N2,027 NXP Semiconductors, TEA5764UK/N2,027 Datasheet - Page 11

• Manufacturer Part Number: TEA5764UK/N2,027
• Description: Tuners FM RADIO WITH RDS
• Manufacturer: NXP Semiconductors

Specifications of TEA5764UK/N2,027

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935278071027 TEA5764UK-G

Philips Semiconductors
TEA5764UK_2
Product data sheet
8.19.1 RDS/RBDS demodulator
8.19.2 RDS data and clock direct
8.16 Software programmable port
8.17 Standby mode
8.18 Power-on reset
8.19 RDS/RBDS
One software programmable port (CMOS output) can be addressed via the I
Bit SWPM = 1, the software port functions as the output for the FRRFLAG.
Bit SWPM = 0, the software port outputs bit SWP of the registers.
In Test mode the software port outputs signals according to
selected, setting bit TM of byte TESTMODE to logic 1.
The software port cannot be disabled by the PUPD bits; see
The radio can be put into Standby mode by the Power-Up / Power-Down (PUPD) bits. The
RDS part can be turned off separately or both the RDS and the FM part can be turned off.
The TEA5764UK is still accessible via the I
supply, in Standby mode, the audio outputs are hard-muted.
After startup of V
registers will be set to their default values. The power-on reset is effectively generated by
V
After a power-on reset the TEA5764UK is in Standby mode and the PUPD bits are set to
logic 0. After a power-on reset the registers are reset to their default value, except for
byte12R to byte19R and flags DAVFLG, LSYNCFLG and PDFLAG. To reset these, the
RDS part must be turned on by setting PUPD. After setting PUPD to logic 1, it will take
0.9 ms to start-up the TEA5764UK and set these registers to their default value.
The power supplies can be switched on in any order.
When the supply voltage V
reference clock input are high-ohmic.
A fully integrated RDS/RBDS demodulator which uses the reference frequency
(32.678 Hz) of the PLL synthesizer tuning system. The RDS demodulator recovers and
regenerates the continuously transmitted RDS or RBDS data stream of the multiplex
signal (MPXRDS) and provides the signals clock (RDCL), data (RDDA) for further
processing by the integrated RDS decoder.
The RDS demodulator retrieves the RDS data and clock signals, this data can be put
directly onto pins VAFL and VAFR by setting bit RDSCDA to logic 1.
CCD
.
CCA
and V
Rev. 02 — 9 August 2005
CCD
CCA
a power-on reset circuit will generate a reset pulse and the
and V
CCD
are at 0 V, all I/Os, the audio outputs and the
2
C-bus but takes only a low power from the
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Table
Section
TEA5764UK
27. Test mode is
8.17.
FM radio + RDS
2
C-bus:
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