STLC5466 STMicroelectronics, STLC5466 Datasheet - Page 77

• Manufacturer Part Number: STLC5466
• Description: RF Wireless Misc Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom ICr

Specifications of STLC5466

• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-176
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

VII.5.2 - Receive Command / Indicate Interrupt when TSV = 1
Time Stamping validated (bit of GCR Register)
These two words are located in the Command/Indicate interrupt queue; IQSR Register indicates the size
of this interrupt queue located in the external memory.
NS
G0
A2/0
C6/1
T15/0 : Binary counter value when a new primitive is occurred.
VII.6 - Receive Monitor Interrupt
VII.6.1 - Receive Monitor Interrupt when TSV = 0
TSV: Time Stamping not Validated (bit of GCR Register)
These two words are transferred into the Monitor interrupt queue; IQSR Register indicates the size of this
interrupt queue located in the external memory.
NS
G0
L
F
bit15
bit15
M18
T15
NS
NS
: New Status.
: G0 = 0, GCI 0 corresponding to DIN4 input and DOUT4 output.
: Last byte
: First byte
: New Status.
: G0 = 0, GCI 0 corresponding to DIN4 input and DOUT4 output.
: COMMAND/INDICATE Channel 0 to 7 being owned by GCI 0 or GCI 1
: New Primitive received twice consecutively
M17
T14
Nu
Before writing the features of event in the external memory the Interrupt Controller reads the NS
bit:
if NS = 0, the Interrupt Controller stores two new bytes M1/8 and M11/18 then puts NS bit at ‘1’
when it writes the status of these two bytes which has been received.
if NS = 1, the Interrupt Controller puts ICOV bit at ‘1’ to generate an interrupt (IR Register).
G0 = 1, GCI 1 corresponding to DIN5 input and DOUT5 output.
L=1, two cases:
if ODD = 1, the following word of the Interrupt Queue contains the Last byte of message.
if ODD =0, the Last byte of message has been stored at the previous access of the Interrupt
Queue (concerning this channel).
L=0, the following word and the previous word does not contain the Last byte of message.
F=1, the following word contains the First byte of message.
F=0, the following word does not contain the First byte of message.
Before writing the features of event in the external memory the Interrupt Controller reads the NS
bit:
if NS = 0, the Interrupt Controller puts this bit at ‘1’ when it writes the new primitive which has
been received.
if NS = 1, the Interrupt Controller puts ICOV bit at ‘1’ to generate an interrupt (IR Register).
When the microprocessor has read the status word, it puts this bit at ‘0’ to acknowledge the new
status. This location becomes free for the Interrupt Controller.
G0 = 1, GCI 1 corresponding to DIN5 input and DOUT5 output.
M16
T13
Nu
M15
T12
Nu
M14
T11
G0
G0
M13
T10
A2
A2
M12
A1
A1
T9
M11
bit8
bit8
A0
T8
A0
bit7
bit7
M8
Nu
T7
M7
Nu
T6
M6
C6
T5
M5
C5
T4
ODD
C4
M4
T3
C3
M3
T2
A
STLC5466
M2
C2
T1
F
77/130
bit 0
bit 0
M1
C1
T0
L