ISPLSI 2064VE-135LT100I LATTICE SEMICONDUCTOR, ISPLSI 2064VE-135LT100I Datasheet - Page 10

• Manufacturer Part Number: ISPLSI 2064VE-135LT100I
• Description: CPLD ispLSI® 2000VE Family 2K Gates 64 Macro Cells 135MHz EECMOS Technology 3.3V 100-Pin TQFP
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPLSI 2064VE-135LT100I

• Package: 100TQFP
• Family Name: ispLSI® 2000VE
• Device System Gates: 2000
• Maximum Propagation Delay Time: 10 ns
• Number Of User I/os: 64
• Number Of Logic Blocks/elements: 16
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 135 MHz
• Operating Temperature: -40 to 85 °C

Power consumption in the ispLSI 2064VE device de-
pends on two primary factors: the speed at which the
device is operating and the number of Product Terms
Figure 3. Typical Device Power Consumption vs fmax
I CC can be estimated for the ispLSI 2064VE using the following equation:
I CC (mA) = 8 + (# of PTs * 0.67) + (# of Nets * Fmax * 0.0045)
Where:
The I CC estimate is based on typical conditions (V CC = 3.3V, room temperature) and an assumption of two GLB
loads on average exists. These values are for estimates only. Since the value of I CC is sensitive to operating
conditions and the program in the device, the actual I CC should be verified.
Power Consumption
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
180
160
140
120
100
80
0
Notes: Configuration of four 16-bit counters
50
Typical current at 3.3V, 25° C
100
ispLSI 2064VE
f
max (MHz)
150
10
used. Figure 3 shows the relationship between power
and operating speed.
Specifications ispLSI 2064VE
200
250
300
0127/2064VE