ISPLSI 2064VE-135LT100I LATTICE SEMICONDUCTOR, ISPLSI 2064VE-135LT100I Datasheet - Page 9

• Manufacturer Part Number: ISPLSI 2064VE-135LT100I
• Description: CPLD ispLSI® 2000VE Family 2K Gates 64 Macro Cells 135MHz EECMOS Technology 3.3V 100-Pin TQFP
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of ISPLSI 2064VE-135LT100I

• Package: 100TQFP
• Family Name: ispLSI® 2000VE
• Device System Gates: 2000
• Maximum Propagation Delay Time: 10 ns
• Number Of User I/os: 64
• Number Of Logic Blocks/elements: 16
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 135 MHz
• Operating Temperature: -40 to 85 °C

Note: Calculations are based on timing specifications for the ispLSI 2064VE-280L.
Derivations of
ispLSI 2064VE Timing Model
GOE 0,1
Ded. In
Y0,1,2
I/O Pin
Reset
(Input)
t
t
t
su
h
co
2.1ns
2.3ns
6.3ns
I/O Delay
=
=
=
=
=
=
=
=
=
=
=
=
#21
#20
t
su,
I/O Cell
Logic + Reg su - Clock (min)
(
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.4 + 0.4 + 2.3) + (0.6) - (0.4 + 0.4 + 0.8)
Clock (max) + Reg h - Logic
(
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.4 + 0.4 + 2.9) + (1.7) - (0.4 + 0.4 + 2.3)
Clock (max) + Reg co + Output
(
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.4 + 0.4 + 2.9) + (0.2) + (1.2 + 1.2)
t
t
t
io +
io +
io +
t
h and
t
t
t
grp +
grp +
grp +
t
t
t
co from the Product Term Clock
t
20ptxor) + (
ptck(max)) + (
ptck(max)) + (
#45
#43, 44
#42
GRP
GRP
#22
t
gsu) - (
t
t
gh) - (
gco) + (
t
io +
t
io +
Reg 4 PT Bypass
t
orp +
#33, 34,
XOR Delays
Control
PTs
t
#25, 26, 27
Feedback
grp +
t
20 PT
35
grp +
#24
Comb 4 PT Bypass #23
9
t
ob)
t
OE
RE
CK
ptck(min))
t
Specifications ispLSI 2064VE
20ptxor)
GLB
GLB Reg Bypass
D
Table 2-0042/2064VE
RST
GLB Reg
Delay
#28
#29, 30,
31, 32
Q
ORP Bypass
Delay
ORP
ORP
#36
#37
#40, 41
0491/2064
#38,
39
I/O Cell
(Output)
I/O Pin