LMX2354TM National Semiconductor, LMX2354TM Datasheet - Page 15

• Manufacturer Part Number: LMX2354TM
• Description: 34C6468
• Manufacturer: National Semiconductor

Specifications of LMX2354TM

• Number Of Elements: 2
• Supply Current: 8.5mA
• Pll Input Freq (min): 10MHz
• Pll Input Freq (max): 2.5GHz
• Operating Supply Voltage (typ): 3V
• Operating Temp Range: -40C to 85C
• Package Type: TSSOP
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Pin Count: 24
• Pll Type: Frequency Synthesis
• Frequency: 2.5GHz
• Supply Voltage Range: 2.7V To 5.5V
• Digital Ic Case Style: TSSOP
• No. Of Pins: 24
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Not Compliant

Programming Description
4.2.1 (RF_R[22]–RF_R[23])
4.2.2 RF_CP_WORD
RF_PD_POL ( RF_R[17] ) should be set to one when RF VCO characteristics are positive. When RF VCO frequency decreases
with increasing control voltage RF_PD_POL should be set to zero.
CP_1X, CP_2X, CP_4X, and CP_8X are used to step the RF Charge Pump output current magnitude from 100 µA to 1.6 mA in
100 µA steps as shown in the table below.
5.0 Programmable Dividers (N Counters)
5.1 IF_N REGISTER
If the Control Bits (CTL [1:0]) are 0 1, data is transferred from the 24-bit shift register into the IF_N register latch which sets the
PLL’s 15-bit programmable N counter value and various control functions. The IF_N counter consists of the 3-bit swallow counter
(A counter), and the 12-bit programmable counter (B counter). Serial data format is shown below in tables 5.1.3 and 5.1.4. The
divide ratio (IF_NB_CNTR) must be
5.1.3. The minimum continuous divide ratio is 56. The CMOS [3:0] bits program the 2 CMOS outputs detailed in section 5.1.2, and
also contain the fractional test bit.
5.1.1 IF_CTL_WORD
Note: See section 5.2.1.2 for IF control word truth table.
Note 1. V2_EN bit when set high enables the voltage doubler for the RF Charge Pump supply.
Note 2. DLL_MODE bit should be set to one for normal usage.
BIT
DLL_MODE
V2_EN
CP_8X
MSB
IF_CTL_WORD [2:0]
23
MSB
IF_CNT_RST
ICPo µA (typ)
1600
100
200
300
400
900
•
•
21 20
LOCATION
RF_R [23]
RF_R [22]
(RF_R[17]–RF_R[21])
CP_4X
CMOS [3:0]
(IF_N[21]–IF_N[23])
RF_R[21]
DLL_MODE
CP8X
3. The divide ratio is programmed using the bits IF_N_CNTR as shown in tables 5.1.2 and
0
0
0
0
1
1
•
•
PWDN_IF
RF Charge Pump Output Truth Table
(Continued)
17 16
FUNCTION
Delay Line Loop
Calibration Mode
RF_Voltage Doubler
Enable
CP_2X
IF_NB_CNTR [11:0]
RF_R[20]
CP4X
15
0
0
0
0
0
1
•
•
5 4
V2_EN
Disabled
CP_1X
IF_NA_CNTR [2:0]
RF_R[19]
PWDN_MODE
CP2X
Slow
0
0
0
1
1
0
1
•
•
2 1
Enabled
RF_PD_POL
0
RF_R[18]
CP1X
Fast
1
0
1
0
1
0
1
•
•
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LSB
LSB
1
0