DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 25

• Manufacturer Part Number: DJLXT6282LE.A3
• Manufacturer: Intel

Specifications of DJLXT6282LE.A3

• Lead Free Status / RoHS Status: Not Compliant

3.1.10.3
3.1.10.4
3.1.10.5
3.1.10.6
Datasheet
The AIS defect alarm status is accessible to the microprocessor via the status registers.
AIS Insert/LOS Alarm filtering
This block includes a filter for Loss Of Signal Alarm input on RLOS pin from the external LIU.
The filtering on the LOS can be integrated over 128 clock cycles or disabled via microprocessor.
An AIS signal (unframed all ones in the data) can be inserted on the incoming data RPOSD and
RNEGD after decoding in case of LOS alarm. DRETCKREF clock reference input (2.048 MHz +/
- 50 ppm) may be used as a blue clock for AIS generation, if the receiver is so configured. The AIS
insert can also be disabled or forced via microprocessor (see configuration register jEH). The AIS
state for every receiver is reported in the global status registers.
Frame Alignment/Out Of Frame Alarm
The framing method follows the rules set forth in CCITT/ITU recommendations G.704 and G.706
and is the same as the one described in the transmitter. Refer to
on page 18
Out Of Frame status changes are indicated via a maskable interrupt, and errored FAS/NFAS (see
global configuration register 0FH) are counted via a 13- bit microprocessor-accessible counter.
CRC-4 Multiframe Alignment/Out of CRC Multiframe Alarm
The multiframe acquisition is the same as in the transmitter. Refer to CRC-4 Multiframe Alignment
on page 14.
Loss Of CRC-4 Multiframe status changes are indicated via a maskable interrupt.
CRC-4 Multiframe Monitoring
CRC-4 Block Errors Calculation
Once the CRC-4 multiframe is acquired, the CRC-4 bits are calculated internally based on a sub-
multiframe (as specified in recommendation ITU G704) and compared to the incoming CRC-4
value in the next sub-multiframe. The block errors are accumulated in a 10-bit counter that can be
read by the microprocessor. A maskable interrupt is provided to indicate counter overflows.
Remote End Block Errors
Two bits per multiframe (RE1 and RE2) are allocated for the CRC-4 Remote End Block Error
(REBE) indication. REBEs are accumulated in a 10-bit counter that can be read by the
microprocessor. A maskable interrupt is provided to indicate counter overflows.
Remote Alarm
The Remote alarm bit (bit 3 in the NFAS) is used to tell the transmit end that the received end has
detected a loss of signal or loss of frame. The remote alarm is filtered for three consecutive frames
before being declared a new value. A change in its status is indicated to the microprocessor via a
maskable interrupt.
and
Figure 5 on page
22.
Section 3.1.2, “Frame Alignment”
LXT6282
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