DJLXT6282LE.A3 Intel, DJLXT6282LE.A3 Datasheet - Page 42

• Manufacturer Part Number: DJLXT6282LE.A3
• Manufacturer: Intel

Specifications of DJLXT6282LE.A3

• Lead Free Status / RoHS Status: Not Compliant

LXT6282
4.3.2
4.3.3
4.3.4
42
Bit <7:5>
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
<7:4>
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit
Unused
BpvOvrFlw
RcvRbeOvrFlw
RcvCrc4ErrOvrFlw
RcvFasErrOvrFlw
Unused
RcvRmtAlm
RcvLomf
RcvOof
RcvAisDet
Los
Name
RCV_ALRM_INT0 - Receiver Alarm Interrupt 0 (j1H)
(j =[8 to F] and corresponds to the E1 channel number)
This register identifies the interrupt source for a particular E1 channel receiver. Each of these bits
can cause the chip interrupt pin to become active if enabled via the bits in the Receive Interrupt
Enable Register j4H.
RCV_ALRM_INT1 - Receiver Alarm Interrupt 1 (j2H)
(j =[8 to F] and corresponds to the E1 channel number)
This register identifies the interrupt source for a particular E1 channel receiver. Each of these bits
can cause the chip interrupt pin to become active if enabled via the bits in the Receive Interrupt
Enable Register j5H.
REC_ALRMS - Receiver Alarm Status (j3H)
(j =[8 to F] and corresponds to the E1 channel number)
This register gives the present status of each alarm source for a particular E1 channel receiver.
Name
This bit is set when there is a change in the RcvRmAlmSt Receive
Remote Alarm bit (j3H). It is cleared when status register (j3H) is read.
This bit is set when there is a change in the RcvLomfSt bit (j3H). It is
cleared when status register (j3H) is read.
This bit is set when there is a change in the RcvOofSt bit (j3H). It is
cleared when status register (j3H) is read.
This bit is set when there is a change in the RcvAisDetSt bit (j3H). It is
cleared when status register (j3H) is read.
This bit is set when there is a change in the LosSt bit (j3H). It is cleared
when status register (i3H) is read.
This bit is set when the BpvCnt[] Code error counter rollover occurs. It
is cleared when this register is read.
This bit is set when the RbeCnt[] Remote Block error counter rollover
occurs. It is cleared when this register is read.
This bit is set when the RcvCrc4ErrCnt[] Receive CRC-4 block error
counter rollover occurs. It is cleared when this register is read.
This bit is set when the RcvFasErrCnt[] Receive Frame Alignment
Signal error counter rollover occurs. It is cleared when this register is
read.
Label
Label
Type
RO
RO
RO
RO
RO
Type
RO
RO
RO
RO
Datasheet
Default
Default
0
0
0
0
0
0
0
0
0