GD82551ER Intel, GD82551ER Datasheet - Page 53

• Manufacturer Part Number: GD82551ER
• Manufacturer: Intel

Specifications of GD82551ER

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Not Compliant

7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
Datasheet
Note: Bit 3 is set to 1b only if the value 00001000b (8h) is written to this register, and bit 4 is set to 1b
PCI Revision ID Register
The Revision ID is an 8-bit read only register. The three least significant bits of the Revision ID can
be overridden by the ID and Revision ID fields in the EEPROM
Interface”). The default values of the Revision ID are:
PCI Class Code Register
The Class Code register is read only and is used to identify the generic function of the device and,
in some cases, specific register level programming interface. The register is broken into three byte
size fields. The upper byte is a base class code and specifies the 82551ER as a network controller,
2h. The middle byte is a subclass code and specifies the 82551ER as an Ethernet controller, 0h. The
lower byte identifies a specific register level programming interface and the 82551ER always
returns a 0h in this field.
PCI Cache Line Size Register
In order for the 82551ER to support the Memory Write and Invalidate (MWI) command, the
82551ER must also support the Cache Line Size (CLS) register in PCI Configuration space. The
register supports only cache line sizes of 8 and 16 Dwords. Any value other than 8 or 16 that is
written to the register is ignored and the 82551ER does not use the MWI command. If a value other
than 8 or 16 is written into the CLS register, the 82551ER returns all zeroes when the CLS register
is read. The figure below shows the format of this register.
only if the value of 00010000b (16h) is written to this register. All other bits are read only and will
return a value of 0b on read.
The BIOS is expected to write to this register. Therefore, the 82551ER driver should not write to it.
PCI Latency Timer
The Latency Timer register is a byte wide register. When the 82551ER is acting as a bus master,
this register defines the amount of time, in PCI clock cycles, that it may own the bus.
PCI Header Type
The Header Type register is a byte read only register and is equal to 00h for a single function NIC
or LOM system. The value of the header type is set by the EEPROM
EEPROM
82551ER (A-step): 0Fh
Figure 16. Cache Line Size Register
Interface”).
7
0
6
0
5
0
RW
4
RW
3
Networking Silicon — 82551ER
(Section 5.5, “Serial EEPROM
2
0
(Section 5.5, “Serial
1
0
0
0
45