GD82551ER Intel, GD82551ER Datasheet - Page 91

• Manufacturer Part Number: GD82551ER
• Manufacturer: Intel

Specifications of GD82551ER

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Not Compliant

11.4.2.2
11.4.2.3
Datasheet
Table 58. PCI Timing Parameters
NOTE: Input test is done with 0.1V
PCI Timings
NOTES:
Flash Interface Timings
The 82551ER is designed to support up to 150 ns of Flash access time. The V
implementation should be connected permanently to 12 V. Thus, writing to the Flash is controlled
only by the FLWE# pin.
Table 59
illustrated in
1. Timing measurement conditions are illustrated in
2. PCI minimum times are specified with loads as detailed in the PCI Bus Specification, Revision 2.1, Section
3. n a PCI environment, REQ# and GNT# are point-to-point signals and have different output valid delay times
4. Timing measurement conditions are illustrated in
5. RST# is asserted and de-asserted asynchronously with respect to the CLK signal.
6. All PCI interface output drivers are floated when RST# is active.
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
4.2.3.2.
and input setup times than bussed signals. All other signals are bussed.
Table 57. Measure and Test Condition Parameters
t
t
t
t
t
t
t
t
T
T
for testing input timing.
Symbol
val
val(ptp)
on
off
su
su(ptp)
h
rst
rst-clk
rst-off
provides the timing parameters for the Flash interface signals. The timing parameters are
Figure 23
PCI CLK to Signal Valid Delay
PCI CLK to Signal Valid Delay (point-
to-point)
Float to Active Delay
Active to Float Delay
Input Setup Time to CLK
PCI Input Setup Time to CLK (point-to-
point)
Input Hold Time from CLK
Reset Active Time After Power Stable
PCI Reset Active Time After CLK
Stable
Reset Active to Output Float Delay
V
V
Input Signal Edge
step
step
(falling edge)
(rising edge)
V
and
Rate
V
max
test
Figure
Parameter
CC
overdrive. V
24.
0.285V
0.615V
0.4V
0.4V
1
CC
CC
max
CC
CC
Figure
Figure
specifies the maximum peak-to-peak waveform allowed
21.
22.
V/ns
V
V
V
V
V
V
Min
100
10
2
2
2
7
0
1
Max Delay
Max Delay
Min Delay
Min Delay
Max
Networking Silicon — 82551ER
11
12
28
40
clocks
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
PP
Notes
1, 2, 3
1, 2, 3
signal in the Flash
3, 4
3, 4
5, 6
1
1
5
5
5
83