PX1011AI-EL1/G NXP Semiconductors, PX1011AI-EL1/G Datasheet
PX1011AI-EL1/G
Specifications of PX1011AI-EL1/G
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PX1011AI-EL1/G Summary of contents
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... The 8-bit data interface operates at 250 MHz with SSTL_2 signaling. The SSTL_2 signaling is compatible with the I/O interfaces available in FPGA products. The PX1011A/1012A PCI Express PHY supports advanced power management functions. The PX1011AI/PX1012AI is for the industrial temperature range ( +85 C). 2. Features 2.1 PCI Express interface I Compliant to PCI Express Base Specifi ...
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... I/O and PVT analog supply voltage 1 for serializer analog supply voltage 2 for serializer reference clock frequency ambient temperature operating commercial industrial Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY Min Typ Max 3.0 3.3 3.6 2.3 2.5 2.7 1.2 1.25 1 ...
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... Ordering information Table 2. Ordering information Type number Solder process PX1011A-EL1 SnPb solder ball compound PX1011A-EL1/G Pb-free (SnAgCu solder ball compound) PX1011AI-EL1/G Pb-free (SnAgCu solder ball compound) PX1012A-EL1/G Pb-free (SnAgCu solder ball compound) PX1012AI-EL1/G Pb-free (SnAgCu solder ball compound) 5. Marking Table 3. Line A ...
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... ENCODE PARALLEL TO SERIAL 250 MHz clock CLK GENERATOR TX I/O REFCLK I/O TX_P TX_N REFCLK_P REFCLK_N Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY PCI Express MAC RXDATA [ 7:0 ] RESET_N PCI Express PHY REGISTER 8 10b/8b DECODE ELASTIC BUFFER 10 K28.5 SERIAL DETECTION ...
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... Fig 2. Pin configuration RXIDLE SS REFCLK_P REFCLK_N RX_P RX_N TX_P TX_N J VREFS Transparent top view. Fig 3. Ball mapping PX1011A_PX1012A_2 Product data sheet PX1011A-EL1 PX1011A-EL1/G PX1011AI-EL1/G PX1012A-EL1/G ball A1 PX1012AI-EL1/G index area Transparent top view RXDATA6 RXDATA4 RXDATA3 RXDATA7 RXDATA5 DDD2 SS DDD2 DDA2 DDA1 V TMS V ...
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... The PHY input and output pins are described in output is defined from the perspective of the PHY. Thus a signal on a pin described as an output is driven by the PHY and a signal on a pin described as an input is received by the PHY. A basic description of each pin is provided. ...
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... PX1011A/PX1012A PCI Express stand-alone X1 PHY Description indicates symbol lock and valid data on RX_DATA and RX_DATAK used to communicate completion of several PHY functions including power management state transitions and receiver detection indicates receiver detection of an electrical idle; this is an asynchronous signal encodes receiver status and error codes for the ...
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... SS 8. Functional description The main function of the PHY is to convert digital data into electrical signals and vice versa. The PCI Express PHY handles the low level PCI Express protocol and signaling. The PX1011A/1012A PCI Express PHY consists of the Physical Coding Sub-layer (PCS), a Serializer and De-serializer (SerDes) and a set of I/Os (pads) ...
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... The PIPE specification recommends that while RESET_N is asserted, the MAC should have RXDET_LOOPB de-asserted, TXIDLE asserted, TXCOMP de-asserted, RXPOL de-asserted and power state P1. The MAC can also assert a reset if it receives a physical layer reset packet. PX1011A_PX1012A_2 Product data sheet PX1011A/PX1012A Rev. 02 — ...
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... P0s state: The MAC will move the PHY to this state only when the transmit channel is idle. While the PHY is in either P0 or P0s power states, if the receiver is detecting an electrical idle, the receiver portion of the PHY can take appropriate power saving measures. Note that the PHY is capable of obtaining bit and symbol lock within the PHY-specifi ...
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... TXIDLE = 1 8.6 Receiver detect When the PHY is in the P1 state, it can be instructed to perform a receiver detection operation to determine if there is a receiver at the other end of the link. Basic operation of receiver detection is that the MAC requests the PHY receiver detect sequence by asserting RXDET_LOOPB. When the PHY has completed the receiver detect sequence, it drives the RXSTATUS signals to the value of 011b if a receiver is present, and to 000b if there is no receiver ...
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... The timing diagram of example, the receiver is receiving a repeating stream of bytes, Rx-a through Rx-z. Similarly, the MAC is causing the PHY to transmit a repeating stream of bytes Tx-a through Tx-z. When the MAC asserts RXDET_LOOPB to the PHY, the PHY begins to loopback the received data to the differential TX_P and TX_N lines. ...
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... Looped back RX data Figure 8 shows an example of timing for entering electrical idle. ScZero COM active (ends with Electrical Idle ordered-set) Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY Junk Junk IDL © Koninklijke Philips Electronics N.V. 2006. All rights reserved. 001aac785 002aac175 ...
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... PHY can add or remove one SKP symbol from each SKP ordered-set as appropriate to manage its elastic buffer. Whenever a SKP symbol is added or removed, the PHY will signal this to the MAC using the RXSTATUS signals. These signals have a non-zero value for one clock cycle and indicate whether a SKP symbol was added or removed from the received SKP ordered-set ...
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... RXSTATUS2, RXSTATUS1, RXSTATUS0 Fig 10. Clock correction - remove a SKP 8.10 Error detection The PHY is responsible for detecting receive errors of several types. These errors are signaled to the MAC layer using the receiver status signals RXSTATUS. Table 15. Operating mode Received data OK One SKP added ...
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... In Figure 11 an 8b/10b decode error. In place of that byte, the PHY places an EDB on the parallel interface, and sets RXSTATUS to the 8b/10b decode error code. Note that a byte that cannot be decoded may also have bad disparity, but the 8b/10b error has precedence. ...
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... In the timing diagram of Figure 14, the PHY is receiving a repeating set of symbols Rx-a through Rx-z. The elastic buffer overflows causing the symbol Rx discarded. The PHY drives RXSTATUS to indicate buffer overflow during the clock cycle when Rx-d would have appeared on the parallel interface ...
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... TRST_N to V PX1011A_PX1012A_2 Product data sheet TXCLK data K28.5 TXCOMP valid data . SS Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY K28.5 K28.5 K28.5 byte transmitted with negative disparity K28.5 K28.5 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. 002aac177 ...
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... Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY Conditions Min for JTAG I/O 0.5 for SSTL_2 I/O 0.5 for core 0.5 for high-speed 0 ...
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... I/O for SSTL_2; no load for core for high-speed serial I/O and PVT for serializer for serializer 1 clock cycle Rev. 02 — 18 May 2006 PCI Express stand-alone X1 PHY Min Typ Max Unit 3.0 3.3 3.6 V 2.3 2.5 2.7 V 1.2 1 ...
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... PLL lock time lock(PLL) t transmitter latency TX_latency t P0s state exit latency P0s_exit_latency t P1 state exit latency P1_exit_latency t RESET_N HIGH to PHYSTATUS LOW time RESET-PHYSTATUS PX1011A_PX1012A_2 Product data sheet PX1011A/PX1012A …continued Conditions 1 clock cycle Rev. 02 — 18 May 2006 PCI Express stand-alone X1 PHY Min ...
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... see Figure 17 see Figure 17 see Figure 17 see Figure 17 TXCLK PXPIPE INPUT t su(TX)(PXPIPE) RXCLK PXPIPE OUTPUT Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY Min Typ Max 249.925 250 250.075 249.925 250 250.075 [1] - 1. 0.68 1. 0.87 500 - - 500 ...
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... nominal V amb DD Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 unit intervals 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 unit intervals © ...
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... 9.1 9.1 0.8 6.4 6.4 0.15 8.9 8.9 REFERENCES JEDEC JEITA MO-205 - - - Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY detail 0.08 0.12 0.1 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2006. All rights reserved. SOT643-1 ISSUE DATE ...
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... July 2004) Volume mm 240 225 Pb-free process - package peak reflow temperatures (from J-STD-020C July 2004) 3 Volume mm < 350 260 260 250 Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY 3 < 350 Volume mm 225 225 Volume mm 350 to Volume mm 2000 260 260 250 ...
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... Suitability of surface mount IC packages for wave and reflow soldering methods [1] [3] , LBGA, LFBGA, SQFP, [3] , TFBGA, VFBGA, XSON , SO, SOJ [8] [9] [8] , PMFP , WQCCN..L Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY Soldering method Wave Reflow not suitable suitable [4] not suitable suitable suitable suitable [5][6] not recommended suitable ...
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... SKP SSTL_2 15. References [1] PCI Express Base Specification — Rev. 1.0a - PCISIG [2] PHY Interface for the PCI Express Architecture (PIPE) Specification Version 1.00 — Intel Corporation PX1011A_PX1012A_2 Product data sheet 10 C measured in the atmosphere of the reflow oven. The package Abbreviations ...
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... Min and Max values for V – added condition “operating” for T – added industrial temperature range • Table 2 “Ordering PX1012A-EL1/G; added industrial temperature range Type numbers PX1011AI-EL1 and PX1012AI-EL1; added column “Soldering compound” • Figure 1 “Block diagram” • ...
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... V”); added Type and Signaling columns supplies”: added Type and Signaling columns; description”: PHY ...” to “The PXPIPE interface between the MAC and PX1011A/1012A ...” data”: data”: “Clocking”: re-written modifi ...
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... and V OH(SSTL2) OL(SSTL2) IH(SSTL2) Preliminary data sheet Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY Change notice Supersedes - PX1011A-EL1_1 interface”: deleted sentence 2 of 3rd paragraph; added modified (appended “I/O”) changed from “V , supply voltage for DD4 ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Rev. 02 — 18 May 2006 PX1011A/PX1012A PCI Express stand-alone X1 PHY © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... Philips Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 PCI Express interface . . . . . . . . . . . . . . . . . . . . 1 2.2 PHY/MAC interface 2.3 JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.4 Power management . . . . . . . . . . . . . . . . . . . . . 2 2.5 Clock 2.6 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 ...