PIC16LF1903-E/MV Microchip Technology, PIC16LF1903-E/MV Datasheet - Page 82

• Manufacturer Part Number: PIC16LF1903-E/MV
• Description: 7KB Flash, 256B RAM, LCD, 11x10b ADC, NanoWatt XLP 28 UQFN 4x4x0.5mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1903-E/MV

• Processor Series: PIC16LF190x
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 4 KB
• Data Ram Size: 256 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-28
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: -
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Eeprom Size: -
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

PIC16LF1902/3
10.2.2
The unlock sequence is a mechanism that protects the
Flash program memory from unintended self-write pro-
gramming or erasing. The sequence must be executed
and completed without interruption to successfully
complete any of the following operations:
• Row Erase
• Load program memory write latches
• Write of program memory write latches to pro-
• Write of program memory write latches to User
The unlock sequence consists of the following steps:
1. Write 55h to PMCON2
2. Write AAh to PMCON2
3. Set the WR bit in PMCON1
4. NOP instruction
5. NOP instruction
Once the WR bit is set, the processor will always force
two NOP instructions. When an Erase Row or Program
Row operation is being performed, the processor will stall
internal operations (typical 2 ms), until the operation is
complete and then resume with the next instruction.
When the operation is loading the program memory write
latches, the processor will always force the two NOP
instructions and continue uninterrupted with the next
instruction.
Since the unlock sequence must not be interrupted,
global interrupts should be disabled prior to the unlock
sequence and re-enabled after the unlock sequence is
completed.
DS41455B-page 82
gram memory
IDs
FLASH MEMORY UNLOCK
SEQUENCE
Preliminary
FIGURE 10-3:
Instruction Fetched ignored
Instruction Fetched ignored
Write or Erase Operation
NOP execution forced
NOP execution forced
Unlock Sequence
Unlock Sequence
Write 0AAh to
Write 055h to
FLASH PROGRAM
MEMORY UNLOCK
SEQUENCE FLOWCHART
PMCON2
PMCON2
(WR = 1)
 2011 Microchip Technology Inc.
Initiate
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