PIC18F26K80-E/MM Microchip Technology, PIC18F26K80-E/MM Datasheet - Page 588

• Manufacturer Part Number: PIC18F26K80-E/MM
• Description: ECAN, 64KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 QFN-S 6x6mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26K80-E/MM

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: ECAN, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.6K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Processor Series: PIC18F26K80
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3648 B
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F66K80 FAMILY
FIGURE 31-21:
TABLE 31-26: A/D CONVERSION REQUIREMENTS
DS39977C-page 588
130
131
132
135
TBD
Note 1:
Param
No.
Note 1:
A/D DATA
SAMPLE
A/D CLK
2:
3:
4:
ADRES
BSF ADCON0, GO
T
T
T
T
T
Symbol
ADIF
AD
CNV
ACQ
SWC
DIS
2:
GO
Q4
The time of the A/D clock period is dependent on the device frequency and the T
ADRES registers may be read on the following T
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (V
On the following cycle of the device clock.
If the A/D clock source is selected as RC, a time of T
be executed.
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
132
A/D Clock Period
Conversion Time
(not including acquisition time)
Acquisition Time
Switching Time from Convert  Sample
Discharge Time
A/D CONVERSION TIMING
(Note 2)
Characteristic
DD
11
(3)
to V
10
SS
or V
OLD_DATA
SS
9
(2)
Preliminary
to V
. . .
SAMPLING STOPPED
CY
DD
is added before the A/D clock starts. This allows the SLEEP instruction to
). The source impedance ( R
CY
. . .
131
130
cycle.
Min
0.8
1.4
1.4
0.2
14
—
—
—
2
(Note 4)
12.5
25
Max
15
—
—
1
3
1
(1)
(1)
Units
T
 s
 s
 s
 s
 s
 s
AD
0
S
 2011 Microchip Technology Inc.
) on the input channels is 50  .
T
V
V
A/D RC mode
V
-40°C to +125°C
-40°C to +125°C
OSC
REF
DD
DD
AD
= 3.0V; T
= 3.0V; A/D RC mode
based, V
full range
clock divider.
NEW_DATA
DONE
Conditions
T
CY
OSC
REF
(Note 1)
based,
 3.0V