PIC18F46J13T-I/PT Microchip Technology, PIC18F46J13T-I/PT Datasheet - Page 154

• Manufacturer Part Number: PIC18F46J13T-I/PT
• Description: 44-pin, GP, 64KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 44 TQFP 10x10
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46J13T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 13x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180030 - BOARD DEMO PIC18F47J13 FS USBMA180029 - BOARD DEMO PIC18F47J53 FS USB
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F47J13 FAMILY
TABLE 10-9:
DS39974A-page 154
RD0/PMD0/
SCL2
RD1/PMD1/
SDA2
RD2/PMD2/
RP19
RD3/PMD3/
RP20
RD4/PMD4/
RP21
RD5/PMD5/
RP22
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; I
Note 1:
Pin
input buffer; x = Don’t care (TRISx bit does not affect port direction or is overridden for this option).
Only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13).
PORTD I/O SUMMARY
Function
PMD0
PMD1
PMD2
PMD3
PMD4
PMD5
SCL2
SDA2
RP19
RP20
RP21
RP22
RD0
RD1
RD2
RD3
RD4
RD5
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Setting
TRIS
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ST/TTL Parallel Master Port data in.
ST/TTL Parallel Master Port data in.
ST/TTL Parallel Master Port data in.
ST/TTL Parallel Master Port data in.
ST/TTL Parallel Master Port data in.
ST/TTL Parallel Master Port data in.
Type
SMB
SMB
DIG
DIG
I
DIG
DIG
DIG
I
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
2
2
Preliminary
C/
C/
PORTD<0> data input.
LATD<0> data output.
Parallel Master Port data out.
I
the module setting.
I
PORTD<1> data input.
LATD<1> data output.
Parallel Master Port data out.
I
the module setting.
I
PORTD<2> data input.
LATD<2> data output.
Parallel Master Port data out.
Remappable Peripheral Pin 19 input.
Remappable Peripheral Pin 19 output.
PORTD<3> data input.
LATD<3> data output.
Parallel Master Port data out.
Remappable Peripheral Pin 20 input.
Remappable Peripheral Pin 20 output.
PORTD<4> data input.
LATD<4> data output.
Parallel Master Port data out.
Remappable Peripheral Pin 21 input.
Remappable Peripheral Pin 21 output.
PORTD<5> data input.
LATD<5> data output.
Parallel Master Port data out.
Remappable Peripheral Pin 22 input.
Remappable Peripheral Pin 22 output.
2
2
2
2
C™ clock input (MSSP2 module); input type depends on
C clock output (MSSP2 module); takes priority over port data.
C data input (MSSP2 module); input type depends on
C data output (MSSP2 module); takes priority over port data.
Description
 2010 Microchip Technology Inc.
2
C/SMB = I
2
C/SMBus