PIC18F46J13T-I/PT Microchip Technology, PIC18F46J13T-I/PT Datasheet - Page 35

• Manufacturer Part Number: PIC18F46J13T-I/PT
• Description: 44-pin, GP, 64KB Flash, 4KB RAM, 12 MIPS, 12-bit ADC, NanoWatt XLP 44 TQFP 10x10
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46J13T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 13x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180030 - BOARD DEMO PIC18F47J13 FS USBMA180029 - BOARD DEMO PIC18F47J53 FS USB
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.0
3.1
Devices in the PIC18F47J13 family incorporate a
different oscillator and microcontroller clock system
than general purpose PIC18F devices.
The PIC18F47J13 family has additional prescalers and
postscalers, which have been added to accommodate a
wide range of oscillator frequencies. The PIC18F47J13
provides two PLL circuits: a 4x multiplier PLL and a
96 MHz PLL enabling 48 MHz operation from the 8 MHz
internal oscillator. Figure 3-1 provides an overview of the
oscillator structure.
Other oscillator features used in PIC18 enhanced
microcontrollers, such as the internal oscillator block
and clock switching, remain the same. They are
discussed later in this chapter.
3.1.1
The operation of the oscillator in PIC18F47J13 family
devices is controlled through three Configuration regis-
ters and two control registers. Configuration registers,
CONFIG1L, CONFIG1H and CONFIG2L, select the
oscillator mode, PLL prescaler and CPU divider
options. As Configuration bits, these are set when the
device is programmed and left in that configuration until
the device is reprogrammed.
The OSCCON register (Register 3-2) selects the Active
Clock mode. It is primarily used in controlling clock
switching in power-managed modes. Its use is
discussed in Section 3.3.1 “Oscillator Control
Register”.
The OSCTUNE register (Register 3-1) is used to trim the
INTOSC frequency source and select the low-frequency
clock source that drives several special features. The
OSCTUNE register is also used to activate or disable the
Phase Locked Loop (PLL). Its use is described in
Section 3.2.5.1 “OSCTUNE Register”.
3.2
PIC18F47J13 family devices can be operated in eight
distinct oscillator modes. Users can program the
FOSC<2:0> Configuration bits to select one of the
modes listed in Table 3-1. For oscillator modes which
produce a clock output (CLKO) on pin, RA6, the output
frequency will be one fourth of the peripheral clock
frequency. The clock output stops when in Sleep mode,
but will continue during Idle mode (see Figure 3-1).
 2010 Microchip Technology Inc.
OSCILLATOR
CONFIGURATIONS
Overview
Oscillator Types
OSCILLATOR CONTROL
Preliminary
PIC18F47J13 FAMILY
TABLE 3-1:
3.2.1
A network of MUXes, clock dividers and two PLL
circuits have been provided, which can be used to
derive various microcontroller frequencies. Figure 3-1
helps in understanding the oscillator structure of the
PIC18F47J13 family of devices.
INTOSCPLLO Internal Oscillator mode, PLL can be
INTOSCPLL Internal Oscillator mode, PLL can be
INTOSCO
INTOSC
ECPLL
HSPLL
Mode
EC
HS
OSCILLATOR MODES
External Clock Input mode, the PLL can
be enabled or disabled in software,
CLKO on RA6, apply external clock
signal to RA7.
always disabled, CLKO on RA6, apply
external clock signal to RA7.
PLL can be enabled or disabled in
software, crystal/resonator connected
between RA6 and RA7.
PLL always disabled, crystal/resonator
connected between RA6 and RA7.
enabled or disabled in software, CLKO
on RA6, port function on RA7, the
internal oscillator block is used to derive
both the primary clock source and the
postscaled internal clock.
enabled or disabled in software, port
function on RA6 and RA7, the internal
oscillator block is used to derive both the
primary clock source and the postscaled
internal clock.
Internal Oscillator mode, PLL is always
disabled, CLKO on RA6, port function on
RA7, the output of the INTOSC
postscaler serves as both the postscaled
internal clock and the primary clock
source.
disabled, port function on RA6 and RA7,
the output of the INTOSC postscaler
serves as both the postscaled internal
clock and the primary clock source.
External Clock Input mode, the PLL is
High-Speed Crystal/Resonator mode,
High-Speed Crystal/Resonator mode,
Internal Oscillator mode, PLL is always
OSCILLATOR MODES
Description
DS39974A-page 35