PIC18F87K90T-I/PT Microchip Technology, PIC18F87K90T-I/PT Datasheet - Page 72

• Manufacturer Part Number: PIC18F87K90T-I/PT
• Description: 128kB Flash, 4kB RAM, 1kB EE, 16MIPS, NanoWatt XLP, LCD, 5V 80 TQFP 12x12x1mm T/
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F87K90T-I/PT

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Timers: 11
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 69
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP
• Lead Free Status / Rohs Status: Details

PIC18F87K90 FAMILY
5.5
The Configuration Mismatch (CM) Reset is designed to
detect, and attempt to recover from, random, memory
corrupting events. These include Electrostatic Discharge
(ESD) events that can cause widespread, single bit
changes throughout the device and result in catastrophic
failure.
In PIC18F87K90 family Flash devices, the device
Configuration registers (located in the configuration
memory space) are continuously monitored during
operation by comparing their values to complimentary
shadow registers. If a mismatch is detected between
the two sets of registers, a CM Reset automatically
occurs. These events are captured by the CM bit
(RCON<5>). The state of the bit is set to ‘0’ whenever
a CM event occurs and does not change for any other
Reset event.
A CM Reset behaves similarly to a Master Clear Reset,
RESET instruction, WDT time-out or Stack Event Reset.
As with all hard and power Reset events, the device
Configuration Words are reloaded from the Flash
Configuration Words, in program memory, as the
device restarts.
FIGURE 5-3:
DS39957D-page 72
INTERNAL RESET
PWRT TIME-OUT
INTERNAL POR
Configuration Mismatch (CM)
MCLR
V
DD
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V
T
PWRT
5.6
PIC18F87K90 family devices incorporate an on-chip
Power-up Timer (PWRT) to help regulate the Power-on
Reset process. The PWRT is enabled by setting the
PWRTEN bit (CONFIG2L<0>). The main function is to
ensure that the device voltage is stable before code is
executed.
The Power-up Timer (PWRT) of the PIC18F87K90
family devices is a 13-bit counter that uses the
LF-INTOSC source as the clock input. This yields an
approximate time interval of 2,048 x 32 s = 66 ms.
While the PWRT is counting, the device is held in
Reset.
The power-up time delay depends on the LF-INTOSC
clock and will vary from chip-to-chip due to temperature
and process variation. See DC Parameter
details.
5.6.1
If enabled, the PWRT time-out is invoked after the POR
pulse has cleared. The total time-out will vary based on
the status of the PWRT.
Figure 5-5
sequences on power-up with the Power-up Timer
enabled.
Since the time-outs occur from the POR pulse, if
MCLR is kept low long enough, the PWRT will expire.
Bringing MCLR high will begin execution immediately
(Figure
synchronizing more than one PIC18 device operating
in parallel.
5-5). This is useful for testing purposes or for
Power-up Timer (PWRT)
TIME-OUT SEQUENCE
and
 2009-2011 Microchip Technology Inc.
Figure 5-6
DD
, V
Figure
DD
all
RISE < T
depict
5-3,
Figure
PWRT
time-out
33
5-4,
)
for