PIC24FJ16MC102-I/SO Microchip Technology, PIC24FJ16MC102-I/SO Datasheet
PIC24FJ16MC102-I/SO
Specifications of PIC24FJ16MC102-I/SO
Related parts for PIC24FJ16MC102-I/SO
PIC24FJ16MC102-I/SO Summary of contents
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... High-Performance, Ultra Low Cost © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 16-bit Microcontrollers Preliminary Data Sheet DS39997B ...
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... Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011, Microchip Technology Incorporated, Printed in the U ...
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... Hz for Center-Aligned mode - PWM frequency for 11-bit resolution (@ 16 MIPS) = 15.63 kHz for Edge-Aligned mode, 7.81 kHz for Center-Aligned mode © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 Power Management: • Single supply on-chip voltage regulator • Switch between clock sources in real time • ...
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... Up to ±16-bit shifts Packaging: • 20-pin PDIP/SOIC/SSOP • 28-pin SPDIP/SOIC/SSOP/QFN • 28-pin QFN: 6x6 mm • 36-pin TLA: 5x5 mm Note: See Table 1 features per device. Preliminary © 2011 Microchip Technology Inc. for the list of peripheral ...
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... The device names, pin counts, memory sizes, and peripheral availability of each device are listed in Table 1. The following pages show their pinout diagrams. TABLE 1: PIC24FJ16MC101/102 CONTROLLER FAMILIES Device PIC24FJ16MC101 PIC24FJ16MC102 Note 1: Two out of three timers are remappable. 2: Two out of three interrupts are remappable. © 2011 Microchip Technology Inc. ...
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... Pins are tolerant DD SS (1) /CN11/RB15 (1) /CN12/RB14 (1) /CN13/RB13 (1) /CN14/RB12 CAP (1) /CN21/RB9 (1) /CN22/RB8 (2) (1) /SCK1/INT0/RP7 /CN23/RB7 DD SS (1) /CN11/RB15 (1) /CN12/RB14 (1) /CN13/RB13 (1) /CN14/RB12 (1) /CN15/RB11 (1) /CN16/RB10 CAP SS (1) /CN21/RB9 (1) /CN22/RB8 (1) /CN23/RB7 (2) (1) /ASCL1/RP6 /CN24/RB6 Table 1 for the list of available Section 15.2 © 2011 Microchip Technology Inc. ...
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... The PWM Fault pins are enabled and asserted during any reset event. Refer to “PWM Faults” for more information on the PWM faults. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 (1) /CN4/RB0 1 (1) /CN5/RB1 2 (1) /CN6/RB2 3 PIC24FJ16MC102 (1) /CN7/RB3 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 Preliminary = Pins are tolerant 22 23 ...
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... SS 3: The PWM Fault pins are enabled and asserted during any reset event. Refer to “PWM Faults” for more information on the PWM faults. DS39997B-page (1) 1 /CN4/RB0 (1) 2 /CN5/RB1 (1) 3 /CN6/RB2 (1) 4 /CN7/RB3 PIC24FJ16MC102 (1) 9 /CN1/RB4 Preliminary = Pins are tolerant ( /CN13/RB13 PWM1L2/RP13 ...
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... Electrical Characteristics .......................................................................................................................................................... 235 27.0 Packaging Information.............................................................................................................................................................. 277 Appendix A: Revision History............................................................................................................................................................. 295 Index ................................................................................................................................................................................................. 297 The Microchip Web Site ..................................................................................................................................................................... 301 Customer Change Notification Service .............................................................................................................................................. 301 Customer Support .............................................................................................................................................................................. 301 Reader Response .............................................................................................................................................................................. 302 Product Identification System ............................................................................................................................................................ 303 © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 Preliminary DS39997B-page 9 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com DS39997B-page 10 to receive the most current information on all of our products. Preliminary © 2011 Microchip Technology Inc. ...
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... Microchip’s dsPIC digital signal controllers. Figure 1-1 shows a general block diagram of the core and peripheral modules in the PIC24FJ16MC101/102 family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 that the Preliminary DS39997B-page 11 ...
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... Address Generator Units EA MUX ROM Latch 16 Instruction Reg Multiplier Register Array Divide Support MCLR OC/ UART1 ADC1 PWM1-2 IC1-IC3 CNx I2C1 Preliminary PORTA PORTB 16 Remappable Pins 16 16 16-bit ALU 16 RTCC PWM 6 Ch “Pin Diagrams” for the specific pins © 2011 Microchip Technology Inc. ...
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... The FLTB1 pin is not available on PIC24FJ16MC101 (20-pin) devices. 3: The PWM Fault pins are enabled during any reset event. Refer to information on the PWM faults. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 Description Analog input channels. External clock source input. Always associated with OSC1 pin function. ...
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... SS Positive supply for peripheral logic and I/O pins. CPU logic filter capacitor connection. Ground reference for logic and I/O pins. Analog = Analog input O = Output Preliminary internally Power I = Input Section 15.2 “PWM Faults” for more © 2011 Microchip Technology Inc. ...
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... Section 32. “High-Level Device Integration” (DS39719) • Section 33. “Programming and Diagnostics” (DS39716) • Section 46. “10-bit Analog-to-Digital Converter (ADC) with 4 Simultaneous Conversions” (DS39737) • Section 47. “Motor Control PWM” (DS39735) • Section 48. “Comparator with Blanking” (DS39741) © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 web site 2 C™ ...
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... PIC24FJ16MC101/102 Notes: DS39997B-page 16 Preliminary © 2011 Microchip Technology Inc. ...
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... Section 2.5 “ICSP Pins”) • OSC1 and OSC2 pins when external oscillator source is used (see Section 2.6 “External Oscillator © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such required. ...
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... Overstress (EOS). Ensure that the MCLR pin Section 26 additional Section 23.2 Preliminary pin provides two specific device and V ) and fast signal shown in Figure 2- Figure 2-2 within EXAMPLE OF MCLR PIN CONNECTIONS R R1 MCLR PIC24F JP C and V specifications are met and V specifications are met. IL © 2011 Microchip Technology Inc. ...
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... REAL ICE™ In-Circuit Debugger User’s Guide” (DS51616) ® • “Using MPLAB REAL ICE™” (poster) (DS51749) © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 2.6 External Oscillator Pins Many MCUs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Configuration” ...
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... Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic-low state. Alternately, connect 10k resistor between V and unused pins. DS39997B-page 20 SS Preliminary © 2011 Microchip Technology Inc. ...
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... The 16th working register (W15) operates as a software Stack Pointer (SP) for interrupts and calls. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 The PIC24FJ16MC101/102 instruction set includes many addressing modes and is designed for optimum ...
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... Control Signals to Various Blocks DS39997B-page 22 X Data Bus Data Latch PCH PCL X RAM Address Loop Control Latch Logic 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg Multiplier Register Array Divide Support Preliminary 16-bit ALU 16 To Peripheral Modules © 2011 Microchip Technology Inc. ...
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... FIGURE 3-2: PIC24FJ16MC101/102 PROGRAMMER’S MODEL PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG — — — — — — SRH © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 D15 D0 W0/WREG W10 W11 W12 W13 W14/Frame Pointer W15/Stack Pointer SPLIM PC0 0 Program Space Visibility Page Address ...
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... The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>). DS39997B-page 24 U-0 U-0 — — (2) R-0 R/W Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (2) Preliminary U-0 U-0 R/W-0 — — DC bit 8 R/W-0 R/W-0 R/W bit 0 © 2011 Microchip Technology Inc. ...
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... Program space visible in data space 0 = Program space not visible in data space bit 1-0 Unimplemented: Read as ‘0’ Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — ...
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... The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. A positive value shifts the operand right. A negative value shifts the operand left. A value of ‘0’ does not modify the operand. Preliminary © 2011 Microchip Technology Inc. ...
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... Manual sections. FIGURE 4-1: PROGRAM MEMORY MAP FOR PIC24FJ16MC101/102 DEVICES Note 1: On reset, these bits are automatically copied into the device Configuration shadow registers. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 The PIC24FJ16MC101/102 separate program and data memory spaces and buses. This architecture also allows the direct access of program memory from the data space during code execution ...
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... Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 7.1 “Interrupt Vector least significant word (lsw Instruction Width Preliminary devices reserve the Table”. PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 © 2011 Microchip Technology Inc. ...
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... Data byte writes only write to the corresponding side of the array or register that matches the byte address. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code ...
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... Optionally Mapped into Program Memory 0xFFFF DS39997B-page 30 LSB 16 bits Address MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x0BFE 0x0C00 0x1FFE 0x2000 0x8000 X Data Unimplemented (X) 0xFFFE Preliminary 8 Kbyte Near Data Space © 2011 Microchip Technology Inc. ...
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TABLE 4-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...
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... CN14PUE CN13PUE CN12PUE CN11PUE CNPU2 — — 006A CN30PUE CN29PUE Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR PIC24FJ16MC102 DEVICES SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr ...
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TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr — — — INTCON1 0080 NSTDIS INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 — — ...
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TABLE 4-5: TIMER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...
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TABLE 4-8: 6-OUTPUT PWM1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 P1TCON 01C0 PTEN — PTSIDL — P1TMR 01C2 PTDIR P1TPER 01C4 — P1SECMP 01C6 SEVTDIR PWM1CON1 01C8 — — — — PWM1CON2 01CA ...
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TABLE 4-10: UART1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr U1MODE 0220 UARTEN — USIDL IREN U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — U1TXREG 0224 — — — — U1RXREG 0226 — — — ...
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TABLE 4-12: ADC1 REGISTER MAP FOR PIC24FJ16MC101 DEVICES File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0300 ADC1BUF0 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA ...
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... TABLE 4-13: ADC1 REGISTER MAP FOR PIC24FJ16MC102 DEVICES File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ADC1BUFC 0318 ...
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TABLE 4-14: CTMU REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 CTMUCON1 033A CTMUEN — CTMUSIDL TGEN CTMUCON2 033C EDG1MOD EDG1POL EDG1SEL<3:0> CTMUICON 033E ITRIM<5:0> Legend unknown value on Reset, — = unimplemented, ...
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TABLE 4-17: COMPARATOR REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 CMSTAT 0650 CMSIDL — — CVRCON 0652 — — — CM1CON 0654 CON COE CPOL CM1MSKSRC 0656 — — — CM1MSKCON 0658 HLMS — ...
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... RPOR7 06CE — — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-20: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR PIC24FJ16MC102 DEVICES File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPOR0 06C0 — ...
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... LATB13 LATB12 ODCB 02CE ODCB15 ODCB14 ODCB13 ODCB12 Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal TABLE 4-23: PORTB REGISTER MAP FOR PIC24FJ16MC102 DEVICES File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name TRISB 02C8 TRISB15 TRISB14 ...
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TABLE 4-24: SYSTEM CONTROL REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RCON 0740 TRAPR IOPUWR — — OSCCON 0742 — COSC<2:0> CLKDIV 0744 ROI DOZE<2:0> OSCTUN 0748 — — — — Legend ...
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... Register Indirect Pre-Modified • 5-bit or 10-bit Literal Note: Not all instructions support all of the addressing Individual instructions different subsets of these addressing modes. Preliminary © 2011 Microchip Technology Inc. Table 4-27 form the addressing modes are modes given above. can support ...
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... Note: Not all instructions support all the addressing modes given above. Individual instructions may support different subsets of these addressing modes. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 Description The address of the file register is specified explicitly. The contents of a register are accessed directly. ...
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... TBLPAG<7:0> 1xxx xxxx xxxx xxxx xxxx xxxx PSVPAG<7:0> xxxx xxxx Preliminary © 2011 Microchip Technology Inc. show how the program EA is <14:1> <0> 0 xxxx xxx0 Data EA<15:0> Data EA<15:0> (1) Data EA<14:0> xxx xxxx xxxx xxxx ...
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... Note 1: The Least Significant bit of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word aligned. Table read operations are permitted in the configuration memory space. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 Program Counter 0 ...
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... TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. 0x800000 Only read operations are shown; write operations are also valid in the user memory area. Preliminary Section 5.0 “Flash © 2011 Microchip Technology Inc. ...
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... PSVPAG is mapped into the upper half of the data memory space... © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘1111 ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed ...
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... PIC24FJ16MC101/102 NOTES: DS39997B-page 50 Preliminary © 2011 Microchip Technology Inc. ...
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... Using 1/0 Table Instruction User/Configuration Space Select © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 ICSP allows a device to be serially programmed while in the end application circuit. This is done with two lines for programming clock and programming data (one of the alternate programming pin pairs: PGECx/PGEDx), and three other lines for power (V Master Clear (MCLR) ...
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... NVMKEY is a write-only register that is used for write protection. To start a programming or erase sequence, the user application must consecutively write 0x55 and 0xAA to the NVMKEY register. Refer to “Programming Operations” 26-12: “DC thereby Preliminary (Register 5-1) controls which Section 5.3 for further details. © 2011 Microchip Technology Inc. ...
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... No operation 1100 = No operation 0011 = Memory word program operation 0010 = No operation 0001 = No operation 0000 = No operation Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 (1) U-0 U-0 — — (1) U-0 R/W-0 — ...
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... NVMKEY<7:0>: Key Register (write-only) bits DS39997B-page 54 U-0 U-0 U-0 — — — W-0 W-0 W-0 NVMKEY<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 W-0 W-0 bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... Regulator V DD Trap Conflict Illegal Opcode Uninitialized W Register Configuration Mismatch © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 • TRAPR: Trap Conflict Reset • IOPUWR: Illegal Condition Device Reset - Illegal Opcode Reset - Uninitialized W Register Reset - Security Reset A simplified block diagram of the Reset module is ...
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... SWDTEN bit setting. DS39997B-page 56 (1) U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary U-0 R/W-0 R/W-0 — CM VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... OST PLL lock time (1.5 ms nominal), if PLL is enabled. LOCK © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 A warm Reset is the result of all other Reset sources, including the RESET instruction. On warm Reset, the device will continue to operate from the current clock source as indicated by the Current Oscillator Selection bits (COSC< ...
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... SYSRST becomes inactive, is long enough to get all operating specification. Preliminary LOCK OST 6 T FSCM 5 Run crosses the DD crosses the V threshold and the DD BOR ) after a BOR. The PWRT Table 6-1. Refer to parameters within © 2011 Microchip Technology Inc. ...
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... V DD SYSRST V dips before PWRT expires SYSRST © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 6.3 BOR and PWRT The on-chip regulator has a BOR circuit that resets the crosses the device when the V DD device operation. The BOR circuit keeps the device in Reset until V delay T has elapsed ...
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... Reset. Note: The configuration mismatch feature and associated Reset flag is not available on all devices. Preliminary Section 23.4 “Watchdog for more information on Watchdog Section 7.0 “Interrupt Controller” for Section 10.0 “I/O © 2011 Microchip Technology Inc. ...
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... SLEEP (RCON<3>) IDLE (RCON<2>) BOR (RCON<1>) POR (RCON<0>) Note: All Reset flag bits can be set or cleared by user software. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 6.9.3 SECURITY RESET If a Program Flow Change (PFC) or Vector Flow Change (VFC) targets a restricted location in a pro- tected segment (Boot and Secure Segment), that operation will cause a security Reset ...
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... PIC24FJ16MC101/102 NOTES: DS39997B-page 62 Preliminary © 2011 Microchip Technology Inc. ...
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... Each interrupt vector contains a 24- bit-wide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR). © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 Interrupt vectors are prioritized in terms of their natural priority. This priority is linked to their position in the vector table ...
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... Table 7-1 for the list of implemented interrupt vectors. DS39997B-page 64 0x000000 0x000002 0x000004 0x000014 ~ ~ ~ 0x00007C Interrupt Vector Table (IVT) 0x00007E 0x000080 ~ ~ ~ 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 ~ ~ ~ Alternate Interrupt Vector Table (AIVT) 0x00017C 0x00017E 0x000180 ~ ~ ~ 0x0001FE 0x000200 Preliminary (1) (1) © 2011 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ16MC101/102 AIVT Address Interrupt Source 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Capture 1 0x000118 OC1 – Output Compare 1 0x00011A T1 – Timer1 0x00011C Reserved 0x00011E IC2 – ...
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... All Interrupt registers are described in through Register 7-27 Preliminary Trap Source Reserved Oscillator Failure Address Error Stack Error Math Error Reserved Reserved Reserved IPCx INTTREG 7-1. For example, the INT0 (External STATUS/CONTROL REGISTERS Register 7-1 in the following pages. © 2011 Microchip Technology Inc. ...
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... CPU interrupt priority level is greater than CPU interrupt priority level less Note 1: For complete register details, see 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 (1) U-0 U-0 — ...
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... Unimplemented: Read as ‘0’ DS39997B-page 68 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 MATHERR ADDRERR STKERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 U-0 OSCFAIL — bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — — — ...
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... Interrupt request has not occurred DS39997B-page 70 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF U-0 R/W-0 R/W-0 — T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1EIF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 Preliminary DS39997B-page 71 ...
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... Interrupt request has not occurred DS39997B-page 72 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 INT1IF CNIF CMPIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 MI2C1IF SI2C1IF bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 9 PWM1IF: PWM1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — — — U-0 ...
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... Interrupt request has not occurred DS39997B-page 74 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2011 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 U1EIF FLTB1IF bit Bit is unknown ...
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... T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE U-0 ...
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... IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS39997B-page 76 Preliminary © 2011 Microchip Technology Inc. ...
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... MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — — — ...
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... U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2011 Microchip Technology Inc. U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown R/W-0 U-0 PWM1IE — ...
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... U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 FLTB1IE: PWM1 Fault B Interrupt Enable bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — — — ...
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... Interrupt is priority 1 000 = Interrupt source is disabled DS39997B-page 80 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC1IP<2:0> bit 8 R/W-0 R/W-0 INT0IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 R/W-0 U-0 R/W-1 — R/W-0 U-0 U-0 — ...
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... Interrupt is priority 1 000 = Interrupt source is disabled DS39997B-page 82 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1IP<2:0> bit 8 R/W-0 R/W-0 T3IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — — — R/W-0 ...
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... Interrupt is priority 1 000 = Interrupt source is disabled DS39997B-page 84 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 CMPIP<2:0> bit 8 R/W-0 R/W-0 SI2C1IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — — — U-0 U-0 R/W-1 — ...
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... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 87
... RTCCIP<2:0>: RTCC Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 R/W-0 U-0 R/W-1 — U-0 U-0 U-0 — ...
Page 88
... Interrupt source is disabled DS39997B-page 88 U-0 U-0 U-0 — — — R/W-0 U-0 R/W-0 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 FLTB1IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 89
... CTMUIP<2:0>: CTMU Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — — — R/W-0 U-0 U-0 — ...
Page 90
... Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 DS39997B-page 90 U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2011 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...
Page 91
... ISR immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 7.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, ...
Page 92
... PIC24FJ16MC101/102 NOTES: DS39997B-page 92 Preliminary © 2011 Microchip Technology Inc. ...
Page 93
... F and F are used interchangeably, except in the case of DOZE mode doze ratio of 1:2 or lower. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 The PIC24FJ16MC101/102 oscillator system provides: • External and internal oscillator options as clock sources • An on-chip 4x Phase-Locked Loop (PLL) to scale the internal operating frequency to the required system clock frequency • ...
Page 94
... MHz are supported by the PIC24FJ16MC101/102 architecture. Instruction execution speed or device operating frequency given by: CY EQUATION 8-1: DEVICE OPERATING FREQUENCY F CY Preliminary © 2011 Microchip Technology Inc. Configuration”. bits, FNOSC<2:0> bits, POSCMD<1:0> Table 8-1. is divided OSC ) and the ...
Page 95
... Primary Oscillator (EC) Fast RC Oscillator (FRC) with Divide-by-n and PLL (FRCPLL) Fast RC Oscillator (FRC) Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 EQUATION 8- Oscillator POSCMD<1:0> Source ...
Page 96
... DS39997B-page 96 (1) R-0 U-0 R/W-y — U-0 R/C-0 U-0 — CF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) OSC (2) ) OSC Preliminary R/W-y R/W-y (2) NOSC<2:0> bit 8 R/W-0 R/W-0 LPOSCEN OSWEN bit Clearable bit x = Bit is unknown © 2011 Microchip Technology Inc. ...
Page 97
... Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 (1) ...
Page 98
... DS39997B-page 98 R/W-1 R/W-0 R/W-0 (2,3) (1,2,3) DOZEN U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2,3) (1,2,3) Preliminary R/W-0 R/W-0 FRCDIV<2:0> bit 8 U-0 U-0 U-0 — — — bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 99
... Center frequency -12% (6.49 MHz) Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — ...
Page 100
... FRCPLL mode are not permitted. This applies to clock switches in either direc- tion. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. to Section 6. “Oscillator” (DS39700) in the “PIC24F Family Reference Manual” for details. © 2011 Microchip Technology Inc. ...
Page 101
... EXAMPLE 9-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 9.2 Instruction-Based Power-Saving Modes PIC24FJ16MC101/102 devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction ...
Page 102
... Similarly PMD bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control regis- ters are already configured to enable module operation). Preliminary There are eight possible © 2011 Microchip Technology Inc. ...
Page 103
... ADC1 module is enabled Note 1: PCFGx bits have no effect if the ADC module is disabled by setting this bit. When the bit is set, all port pins that have been multiplexed with ANx will be in Digital mode. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 R/W-0 R/W-0 U-0 ...
Page 104
... DS39997B-page 104 U-0 U-0 R/W-0 — — IC3MD U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 IC2MD IC1MD bit 8 R/W-0 R/W-0 OC2MD OC1MD bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 105
... Bit is set bit 15-4 Unimplemented: Read as ‘0’ bit 3 CTMUMD: CTMU Module Disable bit 1 = CTMU module is disabled 0 = CTMU module is enabled bit 2-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 R/W-0 — — CMPMD U-0 ...
Page 106
... PIC24FJ16MC101/102 NOTES: DS39997B-page 106 Preliminary © 2011 Microchip Technology Inc. ...
Page 107
... CK WR Port Data Latch Read LAT Read Port © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 provided to a pair of multiplexers. The multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the I/O pin. The logic also prevents “loop through,” in which a port’ ...
Page 108
... CNPU2 registers, which contain the control bits for each of the CN pins. Setting any of the control bits will be OL enables the weak pull-ups for the corresponding pins. Note: Pull-ups on change notification pins should always be disabled when the port pin is configured as a digital output. Preliminary © 2011 Microchip Technology Inc. ...
Page 109
... The association of a peripheral to a peripheral select- able pin is handled in two different ways, depending on whether an input or output is being mapped. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 10.4.2.1 Input Mapping The inputs of the peripheral pin select options are mapped on the basis of the peripheral ...
Page 110
... UPDN Output enable default U1TX Output U1RTS Output 4 OC2 Output UPDN Output Preliminary (1) Configuration Bits INT1R<4:0> INT2R<4:0> T2CKR<4:0> T3CKR<4:0> IC1R<4:0> IC2R<4:0> IC3R<4:0> OCFAR<4:0> U1RXR<4:0> U1CTSR<4:0> SS1R<4:0> MULTIPLEXING OF REMAPPABLE OUTPUT FOR RPn RPnR<4:0> Output enable RPn Output Data 19 26 © 2011 Microchip Technology Inc. ...
Page 111
... IOLOCK remains in one state until changed. This allows all of the peripheral pin selects to be configured with a single unlock sequence followed by an update to all control registers, then locked with a second lock sequence. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 RPn tied to default port pin 00000 RPn tied to Comparator 1 Output ...
Page 112
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary R/W-1 R/W-1 R/W-1 INT1R<4:0> U-0 U-0 U-0 — — — Bit is unknown U-0 U-0 U-0 — — — R/W-1 R/W-1 R/W-1 INT2R<4:0> Bit is unknown © 2011 Microchip Technology Inc. bit 8 bit 0 bit 8 bit 0 ...
Page 113
... T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to the corresponding RPn pin 11111 = Input tied V 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 R/W-1 R/W-1 R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 114
... Input tied to RP1 00000 = Input tied to RP0 DS39997B-page 114 R/W-1 R/W-1 R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 R/W-1 IC2R<4:0> bit 8 R/W-1 R/W-1 R/W-1 IC1R<4:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 115
... OCFAR<4:0>: Assign Output Capture A (OCFA) to the corresponding RPn pin 11111 = Input tied V 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 — — R/W-1 R/W Unimplemented bit, read as ‘0’ ...
Page 116
... Input tied to RP1 00000 = Input tied to RP0 DS39997B-page 116 R/W-1 R/W-1 U1CTSR<4:0> R/W-1 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U1RXR<4:0> Bit is unknown © 2011 Microchip Technology Inc. bit 8 bit 0 ...
Page 117
... SS1R<4:0>: Assign SPI1 Slave Select Input (SS1IN) to the corresponding RPn pin 11111 = Input tied V 01111 = Input tied to RP15 . . . 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 — — R/W-1 R/W Unimplemented bit, read as ‘0’ ...
Page 118
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 10-2 for Table 10-2 for R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 10-2 for Table 10-2 for © 2011 Microchip Technology Inc. ...
Page 119
... RP7R<4:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits (see peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP6R<4:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits (see peripheral function numbers) © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 R/W-0 R/W-0 R/W-0 RP5R<4:0> R/W-0 ...
Page 120
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 10-2 for Table 10-2 for R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 10-2 for Table 10-2 for © 2011 Microchip Technology Inc. ...
Page 121
... RP15R<4:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits (see peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits (see peripheral function numbers) © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 R/W-0 R/W-0 R/W-0 RP13R<4:0> R/W-0 ...
Page 122
... PIC24FJ16MC101/102 NOTES: DS39997B-page 122 Preliminary © 2011 Microchip Technology Inc. ...
Page 123
... SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 Timer1 also supports these features: • Timer gate operation • Selectable prescaler settings • Timer operation during CPU Idle and Sleep modes • Interrupt on 16-bit Period register match or falling ...
Page 124
... DS39997B-page 124 U-0 U-0 — — R/W-0 U-0 TCKPS<1:0> — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) ) Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 (1) TSYNC TCS — bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 125
... T2CON registers are shown in generic form in Register 12-1. T3CON registers are shown in Register 12-2. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 For 32-bit timer/counter operation, Timer2 is the least significant word, and Timer3 is the most significant word (msw) of the 32-bit timers. Note: For 32-bit operation, T3CON control bits are ignored ...
Page 126
... The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register. 2: The ADC event trigger is available only on Timer2/3. DS39997B-page 126 (1) 1x Gate Sync PR3 PR2 Comparator LSb TMR3 TMR2 TMR3HLD 16 Preliminary TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TGATE TCS Sync To CTMU Filter © 2011 Microchip Technology Inc. ...
Page 127
... TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal FIGURE 12-3: TIMER3 (16-BIT) BLOCK DIAGRAM Gate Sync Prescaler F CY TCKPS<1:0> Prescaler Sync (/n) TxCK TCKPS<1:0> To CTMU Filter © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 Gate Sync TMR2 Comparator PR2 Falling Edge Detect 10 (/ TGATE TCS Preliminary TCKPS< ...
Page 128
... DS39997B-page 128 U-0 U-0 — — R/W-0 R/W-0 TCKPS<1:0> T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) Preliminary U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 129
... When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (T2CON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (T2CON<3>), these bits have no effect. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 (1) — ...
Page 130
... PIC24FJ16MC101/102 NOTES: DS39997B-page 130 Preliminary © 2011 Microchip Technology Inc. ...
Page 131
... ICOV, ICBNE (ICxCON<4:3>) ICxCON System Bus Note: An ‘x’ signal, register or bit name denotes the number of the capture channel. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 The Input Capture module captures the 16-bit value of the selected Time Base register when an event occurs at the ICx pin ...
Page 132
... Input capture module turned off DS39997B-page 132 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 133
... TMR3 TMR2 © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 The Output Compare module can select either Timer2 or Timer3 for its time base. The module compares the value of the timer with the value of one or two compare registers depending on the operating mode selected. The state of the output pin changes when the timer value matches the compare register value ...
Page 134
... OCx Falling edge 1 Current output is maintained OCx Rising and Falling edge OCx Falling edge 0 OCx Falling edge OCxR is zero No interrupt 1, if OCxR is non-zero OCFA Falling edge for OC1 to OC4 1, if OCxR is non-zero Timer is reset on period match Preliminary — © 2011 Microchip Technology Inc. ...
Page 135
... Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — ...
Page 136
... PIC24FJ16MC101/102 NOTES: DS39997B-page 136 Preliminary © 2011 Microchip Technology Inc. ...
Page 137
... Fault pins to optionally drive each of the PWM output pins to a defined state • Duty cycle updates configurable to be immediate or synchronized to the PWM time base © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 15.1 PWM1: 6-Channel PWM Module This module simplifies the task of generating multiple synchronized PWM outputs ...
Page 138
... The details of PWM Generator 1 and 2 are not shown for clarity PIC24FJ16MC101 (20-pin) devices, the FLTA1 pin is supported, but requires an external pull-down resistor for correct functionality PIC24FJ16MC102 (28-pin) devices, the FLTA1 and FLTB1 pins are supported and do not require an external pull-down resistor. DS39997B-page 138 PWM Generator 3 P1DC3 Buffer ...
Page 139
... TABLE 15-1: INTERNAL PULL-DOWN RESISTORS ON PWM FAULT PINS Device Fault Pin PIC24FJ16MC101 FLTA1 PIC24FJ16MC102 FLTA1 FLTB1 On devices without internal pull-downs on the Fault pin recommended to connect an external pull-down resistor for Class B safety features. 15.2.1 PWM FAULTS AT RESET During any reset event, the PWM module maintains ownership of both PWM Fault pins ...
Page 140
... Use builtin function to write 0x0000 to P1FLTBCON register __builtin_write_PWMSFR(&P1FLTBCON, 0x0000, &PWM1KEY); // Enable all PWMs using PWM1CON1 register // Writing to PWM1CON1 register requires unlock sequence // Use builtin function to write 0x0077 to PWM1CON1 register __builtin_write_PWMSFR(&PWM1CON1, 0x0077, &PWM1KEY); DS39997B-page 140 Preliminary © 2011 Microchip Technology Inc. ...
Page 141
... PWM time base operates in a Continuous Up/Down Count mode with interrupts for double PWM updates 10 = PWM time base operates in a Continuous Up/Down Count mode 01 = PWM time base operates in Single Pulse mode 00 = PWM time base operates in a Free-Running mode © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — ...
Page 142
... Bit is cleared R/W-0 R/W-0 R/W-0 PTPER<14:8> R/W-0 R/W-0 R/W-0 PTPER<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 143
... A Special Event Trigger will occur when the PWM time base is counting down Special Event Trigger will occur when the PWM time base is counting up bit 14-0 SEVTCMP<14:0>: Special Event Compare Value bits Note 1: SEVTDIR is compared with PTDIR (P 2: PxSECMP<14:0> is compared with P © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 R/W-0 R/W-0 R/W-0 (2) SEVTCMP<14:8> R/W-0 ...
Page 144
... U-0 R/W-0 — — PMOD3 R/W-0 U-0 R/W-0 PEN1H — PEN3L U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Section 15.3 “Write-protected Preliminary R/W-0 R/W-0 PMOD2 PMOD1 bit 8 R/W-0 R/W-0 PEN2L PEN1L bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 145
... Output overrides via the PxOVDCON register occur on next T bit 0 UDIS: PWM Update Disable bit 1 = Updates from Duty Cycle and Period Buffer registers are disabled 0 = Updates from Duty Cycle and Period Buffer registers are enabled © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 R/W-0 R/W-0 — ...
Page 146
... DTA<5:0>: Unsigned 6-bit Dead-Time Value for Dead-Time Unit A bits DS39997B-page 146 R/W-0 R/W-0 R/W-0 DTB<5:0> R/W-0 R/W-0 R/W-0 DTA<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 147
... Dead time provided from Unit Dead time provided from Unit A bit 0 DTS1I: Dead-Time Select for PWM1 Signal Going Inactive bit 1 = Dead time provided from Unit Dead time provided from Unit A © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — — ...
Page 148
... Note 1: On PIC24FJ16MC101 (20-pin) devices, the FLTA1 pin is supported, but requires an external pull-down resistor for correct functionality PIC24FJ16MC102 (28-pin) devices, the FLTA1 and FLTB1 pins are supported and do not require an external pull-down resistor. 3: The PxFLTACON register is a write-protected register. Refer to Registers” ...
Page 149
... Note 1: On PIC24FJ16MC101 (20-pin) devices, the FLTA1 pin is supported, but requires an external pull-down resistor for correct functionality PIC24FJ16MC102 (28-pin) devices, the FLTA1 and FLTB1 pins are supported and do not require an external pull-down resistor. 3: The PxFLTACON register is a write-protected register. Refer to Registers” ...
Page 150
... DS39997B-page 150 R/W-1 R/W-1 R/W-1 POVD3L POVD2H POVD2L R/W-0 R/W-0 R/W-0 POUT3L POUT2H POUT2L U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 POVD1H POVD1L bit 8 R/W-0 R/W-0 POUT1H POUT1L bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 151
... R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 PDC3<15:0>: PWM Duty Cycle 3 Value bits © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 R/W-0 R/W-0 R/W-0 PDC1<15:8> R/W-0 R/W-0 R/W-0 PDC1<7:0> Unimplemented bit, read as ‘0’ ...
Page 152
... Refer to Section 47. “Motor Control PWM” (DS39735) in the “PIC24F Family Reference Manual” for further details about the unlock sequence. DS39997B-page 152 (1) R/W-0 R/W-0 R/W-0 PWMKEY<15:8> R/W-0 R/W-0 R/W-0 PWMKEY<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 153
... SDIx SPIxSR Transfer SPIxRXB SPIxBUF Read SPIxBUF © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 The Serial Peripheral Interface (SPI) module is a syn- chronous serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices can be serial EEPROMs, shift regis- ters, display drivers, analog-to-digital converters, etc. ...
Page 154
... DS39997B-page 154 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2011 Microchip Technology Inc. U-0 U-0 — — bit 8 R-0 R-0 SPITBF SPIRBF bit Bit is unknown ...
Page 155
... The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: This bit must be cleared when FRMEN = not set both Primary and Secondary prescalers to a value of 1:1. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 R/W-0 R/W-0 R/W-0 DISSCK ...
Page 156
... The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). 2: This bit must be cleared when FRMEN = not set both Primary and Secondary prescalers to a value of 1:1. DS39997B-page 156 (3) (3) Preliminary © 2011 Microchip Technology Inc. ...
Page 157
... FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 Unimplemented: This bit must not be set to ‘1’ by the user application. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — ...
Page 158
... PIC24FJ16MC101/102 NOTES: DS39997B-page 158 Preliminary © 2011 Microchip Technology Inc. ...
Page 159
... I C supports multi-master operation, detects bus collision and arbitrates accordingly © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 17.1 Operating Modes The hardware fully implements all the master and slave functions of the I specifications, as well as 7-bit and 10-bit addressing ...
Page 160
... Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSb Reload Control Preliminary Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2011 Microchip Technology Inc. ...
Page 161
... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enable software or receive clock stretching 0 = Disable software or receive clock stretching © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN ...
Page 162
... Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence Start condition not in progress DS39997B-page 162 2 C master, applicable during master receive) C master, applicable during master receive master Hardware clear at end of eighth bit of master receive data byte master master) Preliminary 2 C master) © 2011 Microchip Technology Inc. ...
Page 163
... Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 — — ...
Page 164
... I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. DS39997B-page 164 2 C slave device address byte. Preliminary © 2011 Microchip Technology Inc. ...
Page 165
... AMSKx: Mask for Address bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — ...
Page 166
... PIC24FJ16MC101/102 NOTES: DS39997B-page 166 Preliminary © 2011 Microchip Technology Inc. ...
Page 167
... UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator Hardware Flow Control UART Receiver UART Transmitter © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 The primary features of the UART module are: • Full-Duplex, 8-bit or 9-bit Data Transmission through the UxTX and UxRX pins • Even, Odd Parity Options (for 8-bit data) • ...
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... DS39997B-page 168 MODE REGISTER x R/W-0 R/W-0 U-0 (2) IREN RTSMD R/W-0 R/W-0 R/W-0 URXINV BRGH U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary R/W-0 R/W-0 — UEN<1:0> bit 8 R/W-0 R/W-0 PDSEL<1:0> STSEL bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... Refer to Section 21. “UART” (DS39708) in the “PIC24F Family Reference Manual” for information on enabling the UART module for receive or transmit operation. 2: This feature is only available for the 16x BRG mode (BRGH = 0). © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 MODE REGISTER (CONTINUED) x Preliminary ...
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... U-0 R/W-0 HC — UTXBRK UTXEN R-1 R-0 RIDLE PERR C = Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R-0 R-1 (1) UTXBF TRMT bit 8 R-0 R/C-0 R-0 FERR OERR URXDA bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Refer to Section 21. “UART” (DS39708) in the “PIC24F Family Reference Manual” for information on enabling the UART module for transmit operation. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 STATUS AND CONTROL REGISTER (CONTINUED) x Preliminary ...
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... PIC24FJ16MC101/102 NOTES: DS39997B-page 172 Preliminary © 2011 Microchip Technology Inc. ...
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... Depending on the particular device pinout, the ADC can have up to six analog input pins, designated AN0 through AN5. Block diagrams of the ADC module are shown in Figure 19-1 and Figure 19-2. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 19.2 ADC Initialization To configure the ADC module: 1. Select port (ADxPCFGH< ...
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... CH123NA CH123NB Alternate Input Selection Note 1: Internally connected to CTMU module. 2: This selection is only used with CTMU capacitive and time measurement. DS39997B-page 174 (1) CTMUI Preliminary ADC1BUF0 ADC1BUF1 ADC1BUF2 V V REFH REFL SAR ADC ADC1BUFE ADC1BUFF © 2011 Microchip Technology Inc. ...
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... FIGURE 19-2: ADC1 BLOCK DIAGRAM FOR PIC24FJ16MC102 DEVICES (1) CTMU (2) Open AN0 AN5 Channel Scan CH0SB<4:0> CH0SA<4:0> CH0 CSCNA AN1 AVss CH0NA CH0NB AN0 AN3 CH123SA CH123SB CH1 AVss CH123NA CH123NB AN1 AN4 CH123SA CH123SB CH2 AVss CH123NA CH123NB AN2 AN5 CH123SA ...
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... ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADC Internal (1) RC Clock T CY OSC ( Note 1: See the ADC specifications in DS39997B-page 176 ADxCON3<5:0> 6 ADC Conversion Clock Multiplier 5,..., 64 Section 26.0 “Electrical Characteristics” Preliminary ADxCON3<15> for the exact RC clock value. © 2011 Microchip Technology Inc. ...
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... If ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1. If SSRC = 000, software can write ‘0’ to end sampling and start conversion. If SSRC ≠ 000, automatically cleared by hardware to end sampling and start conversion. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 — ...
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... Automatically set by hardware when ADC conversion is complete. Software can write ‘0’ to clear DONE status (software not allowed to write ‘1’). Clearing this bit will NOT affect any operation in progress. Automatically cleared by hardware at start of a new conversion. DS39997B-page 178 Preliminary © 2011 Microchip Technology Inc. ...
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... Always starts filling buffer from the beginning bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample A on first sample and Sample B on next sample 0 = Always uses channel input selects for Sample A © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 R/W-0 — ...
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... This bit only used if AD1CON1<7:5> (SSRC<2:0> This bit is not used if AD1CON3<15> (ADRC DS39997B-page 180 R/W-0 R/W-0 R/W-0 SAMC<4:0> R/W-0 R/W-0 R/W-0 (2) ADCS<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) ( Preliminary R/W-0 R/W-0 (1) bit 8 R/W-0 R/W-0 bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... CH1 positive input is AN3, CH2 and CH3 positive inputs are not connected 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2 PIC24FJ16MC102 devices only CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5 0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2 © ...
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... Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 PIC24FJ16MC102 devices only: 01110 = No channels connected; all inputs are floating (used for CTMU) 01101 = Channel 0 positive input is connected to CTMU temperature sensor 00101 = Channel 0 positive input is AN5 ...
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... On devices without 6 analog inputs, all AD1CSSL bits can be selected by user application. However, inputs selected for scan without a corresponding input on device converts V 2: CSSx = ANx, where through 5. 3: CTMU temperature sensor input cannot be scanned. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 U-0 — ...
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... U-0 — — R/W-0 R/W-0 (4) (4) (4) PCFG4 PCFG3 PCFG2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (4) Preliminary (1,2,3) U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 R/W-0 (4) (4) (4) PCFG1 PCFG0 bit Bit is unknown SS © 2011 Microchip Technology Inc. ...
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... Refer to Section 4.0 “Memory Organization” this data sheet for device-specific register and bit information. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 The PIC24FJ16MC101/102 Comparator module pro- vides three comparators that can be configured in dif- ferent ways. As shown in comparator options are specified by the Comparator module’ ...
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... Comparator Voltage Reference (Figure 20- Section 26.0 “Electrical Characteristics” Preliminary EVPOL<1:0> Interrupt Logic COE CPOL C1OUT COUT EVPOL<1:0> Interrupt Logic COE CPOL C2OUT COUT EVPOL<1:0> Interrupt Logic COE CPOL C3OUT COUT CV REF for © 2011 Microchip Technology Inc. ...
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... FIGURE 20-3: USER PROGRAMMABLE BLANKING FUNCTION BLOCK DIAGRAM SELSRCA<3:0> MAI Blanking Signals SELSRCB<3:0> MAI MBI MCI Blanking MAI MBI Signals MBI MCI SELSRCC<3:0> Blanking MCI Signals © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 CVRCON<3:0> CV RSRC CVRCON<CVROE> Note 1: This pin Analog Comparator Output ANDI ...
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... PIC24FJ16MC101/102 FIGURE 20-4: DIGITAL FILTER INTERCONNECT BLOCK DIAGRAM Timer2 Timer3 PWM Special Event Trigger F OSC F CY From Blanking Logic DS39997B-page 188 ÷ CFDIV CFSEL<2:0> Digital Filter Preliminary CFLTREN C OUT X © 2011 Microchip Technology Inc. ...
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... C1OUT: Comparator 1 Output Status bit When CPOL = > < When CPOL = < > © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 R-0 — — C3EVT U-0 U-0 R-0 — — C3OUT U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R-0 R-0 C2EVT C1EVT bit 8 R-0 ...
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... Trigger/Event/Interrupt generation is disabled DS39997B-page 190 U-0 U-0 U-0 — — — R/W-0 U-0 U-0 CREF — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 CEVT COUT bit 8 R/W-0 R/W-0 CCH<1:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 1-0 CCH<1:0>: Comparator Channel Select bits input of comparator connects to INTREF input of comparator connects input of comparator connects input of comparator connects © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 + input) IN voltage REFIN IND pin X INC pin X INB pin X Preliminary DS39997B-page 191 ...
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... PWM1H2 0010 = PWM1L2 0001 = PWM1H1 0000 = PWM1L1 DS39997B-page 192 U-0 R/W-0 R/W-0 — SELSRCC<3:0> R/W-0 R/W-0 R/W-0 SELSRCA<3:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 RW-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... Reserved 1110 = Reserved 1101 = Reserved 1100 = Reserved 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Reserved 0111 = Reserved 0110 = Reserved 0101 = PWM1H3 0100 = PWM1L3 0011 = PWM1H2 0010 = PWM1L2 0001 = PWM1H1 0000 = PWM1L1 © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 Preliminary DS39997B-page 193 ...
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... DS39997B-page 194 R/W-0 R/W-0 R/W-0 OCNEN OBEN OBNEN R/W-0 R/W-0 R/W-0 ACNEN ABEN ABNEN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OAEN OANEN bit 8 R/W-0 R/W-0 AAEN AANEN bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... AAEN: AND Gate A1 A Input Enable bit 1 = MAI is connected to AND gate 0 = MAI is not connected to AND gate bit 0 AANEN: AND Gate A1 A Input Inverted Enable bit 1 = Inverted MAI is connected to AND gate 0 = Inverted MAI is not connected to AND gate © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 Preliminary DS39997B-page 195 ...
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... Clock Divide 1:1 DS39997B-page 196 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 CFLTREN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 I-0 — — bit 8 R/W-0 R/W-0 CFDIV<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... CV REFIN RSRC Note 1: CVROE overrides the TRIS bit setting. 2: This reference voltage is generated internally on the device. Refer to Characteristics” for the specified voltage range. © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 U-0 U-0 — — VREFSEL U-0 R/W-0 — ...
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... PIC24FJ16MC101/102 NOTES: DS39997B-page 198 Preliminary © 2011 Microchip Technology Inc. ...
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... Alarm Event Comparator Compare Registers with Masks Repeat Counter © 2011 Microchip Technology Inc. PIC24FJ16MC101/102 Some of the key features of the RTCC module are: • Time: hours, minutes, and seconds • 24-hour format (military time) • Calendar: weekday, date, month and year • ...
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... For the RTCWREN bit to be set, there is only 1 instruction cycle time window allowed between the 55h/AA sequence and the setting of RTCWREN; therefore recommended that code follow the procedure in Example 21-1. © 2011 Microchip Technology Inc. ...