PIC24FV16KA301-E/P Microchip Technology, PIC24FV16KA301-E/P Datasheet - Page 119

16KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 12-bit ADC, CTMU, 5V 20 PDIP .300in T

PIC24FV16KA301-E/P

Manufacturer Part Number
PIC24FV16KA301-E/P
Description
16KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 12-bit ADC, CTMU, 5V 20 PDIP .300in T
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheet

Specifications of PIC24FV16KA301-E/P

Processor Series
PIC24FV
Core
PIC
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
16 KB
Data Ram Size
2 KB
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Package / Case
PDIP-20
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
512 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Lead Free Status / Rohs Status
 Details
9.3
The operation of the oscillator is controlled by three
Special Function Registers (SFRs):
• OSCCON
• CLKDIV
• OSCTUN
The OSCCON register
control register for the oscillator. It controls clock
source switching and allows the monitoring of clock
sources.
REGISTER 9-1:
 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
HS = Hardware Settable bit
R = Readable bit
-n = Value at POR
bit 15
bit 14-12
bit 11
bit 10-8
Note 1:
R/SO-0, HSC
CLKLOCK
U-0
2:
3:
Control Registers
Reset values for these bits are determined by the FNOSC Configuration bits.
Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.
When SOSC is selected to run from a digital clock input, rather than an external crystal (SOSCSRC = 0),
this bit has no effect.
Unimplemented: Read as ‘0’
COSC<2:0>: Current Oscillator Selection bits
111 = 8 MHz Fast RC Oscillator with Postscaler (FRCDIV)
110 = 500 kHz Low-Power Fast RC Oscillator (FRC) with Postscaler (LPFRCDIV)
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = 8 MHz FRC Oscillator with Postscaler and PLL module (FRCPLL)
000 = 8 MHz FRC Oscillator (FRC)
Unimplemented: Read as ‘0’
NOSC<2:0>: New Oscillator Selection bits
111 = 8 MHz Fast RC Oscillator with Postscaler (FRCDIV)
110 = 500 kHz Low-Power Fast RC Oscillator (FRC) with Postscaler (LPFRCDIV)
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = 8 MHz FRC Oscillator with Postscaler and PLL module (FRCPLL)
000 = 8 MHz FRC Oscillator (FRC)
R-0, HSC
COSC2
OSCCON: OSCILLATOR CONTROL REGISTER
U-0
(Register
HSC = Hardware Settable/Clearable bit
CO = Clearable Only bit
W = Writable bit
‘1’ = Bit is set
R-0, HSC
9-1) is the main
R-0, HSC
COSC1
LOCK
(2)
PIC24FV32KA304 FAMILY
R-0, HSC
COSC0
U-0
(1)
The Clock Divider register
features associated with Doze mode, as well as the
postscaler for the FRC oscillator.
The FRC Oscillator Tune register
the user to fine tune the FRC oscillator over a range of
approximately ±5.25%. Each bit increment or decre-
ment changes the factory calibrated frequency of the
FRC oscillator by a fixed amount.
SO = Settable Only bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/CO-0, HS
U-0
CF
SOSCDRV
R/W-x
R/W-0
NOSC2
(1)
(3)
(Register
x = Bit is unknown
SOSCEN
R/W-x
NOSC1
R/W-0
(Register
DS39995B-page 119
9-2) controls the
(1)
9-3) allows
R/W-x
OSWEN
NOSC0
R/W-0
bit 8
bit 0
(1)

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