PIC24FV16KA301-E/P Microchip Technology, PIC24FV16KA301-E/P Datasheet - Page 128

• Manufacturer Part Number: PIC24FV16KA301-E/P
• Description: 16KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 12-bit ADC, CTMU, 5V 20 PDIP .300in T
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FV16KA301-E/P

• Processor Series: PIC24FV
• Core: PIC
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 16 KB
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Package / Case: PDIP-20
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 17
• Eeprom Size: 512 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

PIC24FV32KA304 FAMILY
10.2.2
Idle mode has these features:
• The CPU will stop executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By
• If the WDT or FSCM is enabled, the LPRC will
The device will wake from Idle mode on any of these
events:
• Any interrupt that is individually enabled
• Any device Reset
• A WDT time-out
On wake-up from Idle, the clock is re-applied to the
CPU and instruction execution begins immediately,
starting with the instruction following the PWRSAV
instruction or the first instruction in the ISR.
10.2.3
Any interrupt that coincides with the execution of a
PWRSAV instruction will be held off until entry into Sleep
or Idle mode has completed. The device will then
wake-up from Sleep or Idle mode.
10.2.4
In PIC24FV32KA304 family devices, Deep Sleep mode
is intended to provide the lowest levels of power
consumption available without requiring the use of
external switches to completely remove all power from
the device. Entry into Deep Sleep mode is completely
under software control. Exit from Deep Sleep mode can
be triggered from any of the following events:
• POR event
• MCLR event
• RTCC alarm (If the RTCC is present)
• External Interrupt 0
• Deep Sleep Watchdog Timer (DSWDT) time-out
• Ultra Low-Power Wake-up (ULPWU) Event
In Deep Sleep mode, it is possible to keep the device
Real-Time Clock and Calendar (RTCC) running without
the loss of clock cycles.
The device has a dedicated Deep Sleep Brown-out
Reset (DSBOR) and a Deep Sleep Watchdog Timer
Reset (DSWDT) for monitoring voltage and time-out
events. The DSBOR and DSWDT are independent of
the standard BOR and WDT used with other
power-managed modes (Sleep, Idle and Doze).
DS39995B-page 128
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see
“Selective Peripheral Module
also remain active.
IDLE MODE
INTERRUPTS COINCIDENT WITH
POWER SAVE INSTRUCTIONS
DEEP SLEEP MODE
Control”).
Section 10.6
10.2.4.1
Deep Sleep mode is entered by setting the DSEN bit in
the DSCON register, and then executing a Sleep
command (PWRSAV
sequence is required to set the DSEN bit. Once the
DSEN bit has been set, there is no time limit before the
SLEEP command can be executed. The DSEN bit is
automatically cleared when exiting the Deep Sleep
mode.
The sequence to enter Deep Sleep mode is:
1.
2.
3.
4.
5.
6.
Any time the DSEN bit is set, all bits in the DSWAKE
register will be automatically cleared.
To set the DSEN bit, the unlock sequence in
Example 10-2
EXAMPLE 10-2:
//Disable Interrupts For 5 instructions
asm volatile(“disi #5”);
//Issue Unlock Sequence
asm volatile
mov #0x55, W0;
mov W0, NVMKEY;
mov #0xAA, W1;
mov W1, NVMKEY;
bset
Note:
Note:
If the application requires the Deep Sleep WDT,
enable it and configure its clock source. For
more information on Deep Sleep WDT, see
Section 10.2.4.5 “Deep Sleep
If the application requires Deep Sleep BOR,
enable it by programming the DSLPBOR
Configuration bit (FDS<6>).
If the application requires wake-up from Deep
Sleep on RTCC alarm, enable and configure the
RTCC module For more information on RTCC,
see
Calendar
If needed, save any critical application context
data by writing it to the DSGPR0 and DSGPR1
registers (optional).
Enable Deep Sleep mode by setting the DSEN
bit (DSCON<15>).
Enter Deep Sleep mode by issuing a PWRSAV #0
instruction.
DSCON, #DSEN
Section 19.0 “Real-Time Clock and
To re-enter Deep Sleep after a Deep Sleep
wake-up, allow a delay of at least 3 T
after clearing the RELEASE bit.
An unlock sequence is required to set the
DSEN bit.
Entering Deep Sleep Mode
is required:
(RTCC)”.
THE UNLOCK SEQUENCE
 2011 Microchip Technology Inc.
#SLEEP_MODE). An unlock
WDT”.
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