PIC24FV16KA301-E/P Microchip Technology, PIC24FV16KA301-E/P Datasheet - Page 120

• Manufacturer Part Number: PIC24FV16KA301-E/P
• Description: 16KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 12-bit ADC, CTMU, 5V 20 PDIP .300in T
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FV16KA301-E/P

• Processor Series: PIC24FV
• Core: PIC
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 16 KB
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Package / Case: PDIP-20
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 17
• Eeprom Size: 512 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

PIC24FV32KA304 FAMILY
REGISTER 9-1:
DS39995B-page 120
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
3:
Reset values for these bits are determined by the FNOSC Configuration bits.
Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.
When SOSC is selected to run from a digital clock input, rather than an external crystal (SOSCSRC = 0),
this bit has no effect.
CLKLOCK: Clock Selection Lock Enabled bit
If FSCM is enabled (FCKSM1 = 1):
1 = Clock and PLL selections are locked
0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit
If FSCM is disabled (FCKSM1 = 0):
Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.
Unimplemented: Read as ‘0’
LOCK: PLL Lock Status bit
1 = PLL module is in lock or PLL module start-up timer is satisfied
0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled
Unimplemented: Read as ‘0’
CF: Clock Fail Detect bit
1 = FSCM has detected a clock failure
0 = No clock failure has been detected
SOSCDRV: Secondary Oscillator Drive Strength bit
1 = High-power SOSC circuit selected
0 = Low/high-power select is done via the SOSCSRC Configuration bit
SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit
1 = Enable secondary oscillator
0 = Disable secondary oscillator
OSWEN: Oscillator Switch Enable bit
1 = Initiate an oscillator switch to clock source specified by NOSC<2:0> bits
0 = Oscillator switch is complete
OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
(2)
(3)
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