S25FL129P0XNFI000 Spansion Inc., S25FL129P0XNFI000 Datasheet - Page 14

• Manufacturer Part Number: S25FL129P0XNFI000
• Description: IC128M CMOS 3V 104MHZ SPI SERIAL PERIP INTERFACE
• Manufacturer: Spansion Inc.

7. Device Operations
7.1
7.2
7.3
7.4
7.5
7.6
14
Byte or Page Programming
Quad Page Programming
Dual and Quad I/O Mode
Sector Erase / Bulk Erase
Monitoring Write Operations Using the Status Register
Active Power and Standby Power Modes
All Spansion SPI devices accept and output data in bytes (8 bits at a time). The SPI device is a slave device
that supports an inactive clock while CS# is held low.
Programming data requires two commands: Write Enable (WREN), which is one byte, and a Page Program
(PP) sequence, which consists of four bytes plus data. The Page Program sequence accepts from 1 byte up
to 256 consecutive bytes of data (which is the size of one page) to be programmed in one operation.
Programming means that bits can either be left at 0, or programmed from 1 to 0. Changing bits from 0 to 1
requires an erase operation.
The Quad Page Program (QPP) instruction allows up to 256 bytes of data to be programmed using 4 pins as
inputs at the same time, thus effectively quadrupling the data transfer rate, compared to the Page Program
(PP) instruction. The Write Enable Latch (WEL) bit must be set to a 1 using the Write Enable (WREN)
command prior to issuing the QPP command.
The S25FL129P device supports Dual and Quad I/O operation when using the Dual/Quad Output Read Mode
and the Dual/Quad I/O High Performance Mode instructions. Using the Dual or Quad I/O instructions allows
data to be transferred to or from the device at two to four times the rate of standard SPI devices. When
operating in the Dual or Quad I/O High Performance Mode (BBh or EBh instructions), data can be read at fast
speed using two or four data bits at a time, and the 3-byte address can be input two or four address bits at a
time.
The Sector Erase (SE) and Bulk Erase (BE) commands set all the bits in a sector or the entire memory array
to 1. While bits can be individually programmed from 1 to 0, erasing bits from 0 to 1 must be done on a sector-
wide (SE) or array-wide (BE) level. In addition to the 64-KB Sector Erase (SE), the S25FL129P device also
offers 4-KB Parameter Sector Erase (P4E) and 8-KB Parameter Sector Erase (P8E) (only applicable for the
uniform 64 KB sector device).
The host system can determine when a Write Register, program, or erase operation is complete by
monitoring the Write in Progress (WIP) bit in the Status Register. The Read from Status Register command
provides the state of the WIP bit. In addition, the S25FL129P device offers two additional bits in the Status
Register (P_ERR, E_ERR) to indicate whether a Program or Erase operation was a success or failure.
The device is enabled and in the Active Power mode when Chip Select (CS#) is Low. When CS# is high, the
device is disabled, but may still be in the Active Power mode until all program, erase, and Write Registers
operations have completed. The device then goes into the Standby Power mode, and power consumption
drops to I
signals. After writing the DP command, the device ignores any further program or erase commands, and
reduces its power consumption to I
SB
. The Deep Power-Down (DP) command provides additional data protection against inadvertent
D a t a
DP
.
S25FL129P
S h e e t
( P r e l i m i n a r y )
S25FL129P_00_04 November 2, 2009