SST25VF512A-33-4I-QAE-T Microchip Technology, SST25VF512A-33-4I-QAE-T Datasheet - Page 13

• Manufacturer Part Number: SST25VF512A-33-4I-QAE-T
• Description: 2.7V To 3.6V 512Kbit SPI Serial Flash 8 TDFN-S 6x5x0.8mm T/R
• Manufacturer: Microchip Technology

Specifications of SST25VF512A-33-4I-QAE-T

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 512K (64K x 8)
• Speed: 33MHz
• Interface: SPI Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-WDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

512 Kbit SPI Serial Flash
SST25VF512A
Sector-Erase
The Sector-Erase instruction clears all bits in the selected 4
KByte sector to FFH. A Sector-Erase instruction applied to
a protected memory area will be ignored. Prior to any Write
operation, the Write-Enable (WREN) instruction must be
executed. CE# must remain active low for the duration of
the any command sequence. The Sector-Erase instruction
is initiated by executing an 8-bit command, 20H, followed
by address bits [A
Block-Erase
The Block-Erase instruction clears all bits in the selected 32
KByte block to FFH. A Block-Erase instruction applied to a
protected memory area will be ignored. Prior to any Write
operation, the Write-Enable (WREN) instruction must be
executed. CE# must remain active low for the duration of
any command sequence. The Block-Erase instruction is
initiated by executing an 8-bit command, 52H or D8H, fol-
lowed by address bits [A
©2006 Silicon Storage Technology, Inc.
FIGURE 8: S
FIGURE 9: B
ECTOR
LOCK
23
-E
-A
-E
RASE
23
0
RASE
]. Address bits [A
-A
SCK
SCK
CE#
CE#
0
SO
SO
]. Address bits [A
SI
SI
S
S
EQUENCE
EQUENCE
MODE 3
MODE 0
MODE 3
MODE 0
MSB
MSB
0 1 2 3 4 5 6 7 8
0 1 2 3 4 5 6 7 8
52 or D8
MS
MS
20
-A
-A
HIGH IMPEDANCE
12
HIGH IMPEDANCE
15
]
]
13
MSB
MSB
(A
sector address (SA
V
cuted. The user may poll the Busy bit in the software status
register or wait T
timed Sector-Erase cycle. See Figure 8 for the Sector-
Erase sequence.
(A
block address (BA
V
cuted. The user may poll the Busy bit in the software status
register or wait T
timed Block-Erase cycle. See Figure 9 for the Block-Erase
sequence.
ADD.
ADD.
IH.
IH
MS
MS
. CE# must be driven high before the instruction is exe-
CE# must be driven high before the instruction is exe-
= Most Significant address) are used to determine the
= Most significant address) are used to determine
15 16
15 16
ADD.
ADD.
23 24
23 24
SE
BE
X
ADD.
ADD.
X
), remaining address bits can be V
), remaining address bits can be V
for the completion of the internal self-
for the completion of the internal self-
1264 F09.0
1264 F08.0
31
31
S71264-02-000
Data Sheet
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