SST25VF512A-33-4I-QAE-T Microchip Technology, SST25VF512A-33-4I-QAE-T Datasheet - Page 8

• Manufacturer Part Number: SST25VF512A-33-4I-QAE-T
• Description: 2.7V To 3.6V 512Kbit SPI Serial Flash 8 TDFN-S 6x5x0.8mm T/R
• Manufacturer: Microchip Technology

Specifications of SST25VF512A-33-4I-QAE-T

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 512K (64K x 8)
• Speed: 33MHz
• Interface: SPI Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-WDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Sheet
Instructions
Instructions are used to Read, Write (Erase and Program),
and configure the SST25VF512A. The instruction bus
cycles are 8 bits each for commands (Op Code), data, and
addresses. Prior to executing any Byte-Program, Auto
Address Increment (AAI) programming, Sector-Erase,
Block-Erase, or Chip-Erase instructions, the Write-Enable
(WREN) instruction must be executed first. The complete
list of the instructions is provided in Table 6. All instructions
are synchronized off a high to low transition of CE#. Inputs
will be accepted on the rising edge of SCK starting with the
TABLE 6: D
©2006 Silicon Storage Technology, Inc.
Bus Cycle
Cycle Type/Operation
Read (20 MHz)
High-Speed-Read (33 MHz)
Sector-Erase
Block-Erase
Chip-Erase
Byte-Program
Auto Address Increment
(AAI) Program
Read-Status-Register
(RDSR)
Enable-Write-Status-Register
(EWSR)
Write-Status-Register
(WRSR)
Write-Enable (WREN)
Write-Disable (WRDI)
Read-ID
10. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of
11. Manufacturer’s ID is read with A
12. Device ID = 48H for SST25VF512A
1. A
2. One bus cycle is eight clock periods.
3. Operation: S
4. X = Dummy Input Cycles (V
5. Sector addresses: use A
6. Prior to any Byte-Program, AAI-Program, Sector-Erase, Block-Erase, or Chip-Erase operation, the Write-Enable (WREN) instruction
7. Block addresses for: use A
8. To continue programming to the next sequential address location, enter the 8-bit command, AFH,
9. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
A
Address bits above the most significant bit of each density can be V
must be executed.
followed by the data to be programmed.
each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both
instructions effective.
ID output stream is continuous until terminated by a low to high transition on CE#
MS
MS
10
10
= A
= Most Significant Address
6
5,7
2
5,6
15
6
6,8
for SST25VF512A
EVICE
IN
= Serial In, S
O
3,4
PERATION
MS
52H or
60H or
90H or
MS
-A
ABH
0BH
D8H
C7H
AFH
03H
20H
02H
05H
50H
01H
06H
04H
IL
S
OUT
12
-A
IN
or V
, remaining addresses can be V
15
0
= Serial Out
=0, and Device ID is read with A
1
, remaining addresses can be V
I
IH
NSTRUCTIONS
); - = Non-Applicable Cycles (Cycles are not necessary)
S
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
OUT
A
A
A
A
A
A
Data
23
23
23
23
23
23
00H
S
X
-A
-A
-A
-A
-
-A
-A
-
-
-
IN
16
16
16
16
16
16
1
2
S
D
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
OUT
OUT
-
-
-
-
A
A
A
A
A
A
IL
8
00H
S
15
15
15
15
15
15
0
or V
IL
=1. All other address bits are 00H. The Manufacturer’s and Device
-
-
-
-
-
-
IN
-A
-A
-A
-A
-A
-A
or V
IL
most significant bit. CE# must be driven low before an
instruction is entered and must be driven high after the last
bit of the instruction has been shifted in (except for Read,
Read-ID and Read-Status-Register instructions). Any low
to high transition on CE#, before receiving the last bit of an
instruction bus cycle, will terminate the instruction in
progress and return the device to the standby mode.
Instruction commands (Op Code), addresses, and data are
all input from the most significant bit (MSB) first.
8
8
8
8
8
8
IH
or V
3
IH
S
Note
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
IH
OUT
-
-
-
-
-
9
ID Addr
A
A
A
A
A
A
S
7
7
7
7
7
7
-.
-A
-A
-A
-A
-
-A
-A
-
-
-
-
IN
0
0
0
0
0
0
11
4
512 Kbit SPI Serial Flash
S
Note
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
OUT
-
-
-
-
-
9
S
D
D
X
X
X
-
-
-
-
-
-
-
-
IN
IN
IN
5
D
S
Note
D
Hi-Z
Hi-Z
OUT
OUT
OUT
X
-
-
-
-
-
-
-
SST25VF512A
12
9
S71264-02-000
S
D
D
X
X
IN
IN
IN
6
D
T6.0 1264
S
Note
D
Hi-Z
Hi-Z
OUT
OUT
OUT
12
1/06
9