STM8L151G4Y6TR STMicroelectronics, STM8L151G4Y6TR Datasheet - Page 56

• Manufacturer Part Number: STM8L151G4Y6TR
• Description: 8 BITS MICROCONTR
• Manufacturer: STMicroelectronics
• Series: STM8L EnergyLiter

Specifications of STM8L151G4Y6TR

• Core Processor: STM8
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, IR, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 18x12b, D/A 1x12
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-UFBGA, CSPBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Option bytes
Table 13.
56/122
Option
OPT0
OPT1
OPT2
OPT3
OPT4
byte
No.
ROP[7:0] Memory readout protection (ROP)
UBC[7:0] Size of the user boot code area
Reserved
IWDG_HW: Independent watchdog
IWDG_HALT: Independent window watchdog off on Halt/Active-halt
WWDG_HW: Window watchdog
WWDG_HALT: Window window watchdog reset on Halt/Active-halt
HSECNT: Number of HSE oscillator stabilization clock cycles
LSECNT: Number of LSE oscillator stabilization clock cycles
Refer to
Option byte description
0xAA: Disable readout protection (write access via SWIM protocol)
Refer to Readout protection section in the STM8L15x and STM8L16x reference manual (RM0031).
0x00: no UBC
0x01: the UBC contains only the interrupt vectors.
0x02: Page 0 and 1 reserved for the UBC and read/write protected. Page 0 contains only the interrupt
vectors.
0x03 - Page 0 to 2 reserved for UBC, memory write-protected
0xFF - Page 0 to 254 reserved for UBC, memory write-protected
Refer to User boot code section in the STM8L15x and STM8L16x reference manual (RM0031).
0: Independent watchdog activated by software
1: Independent watchdog activated by hardware
0: Independent watchdog continues running in Halt/Active-halt mode
1: Independent watchdog stopped in Halt/Active-halt mode
0: Window watchdog activated by software
1: Window watchdog activated by hardware
0: Window watchdog stopped in Halt mode
1: Window watchdog generates a reset when MCU enters Halt mode
0x00 - 1 clock cycle
0x01 - 16 clock cycles
0x10 - 512 clock cycles
0x11 - 4096 clock cycles
0x00 - 1 clock cycle
0x01 - 16 clock cycles
0x10 - 512 clock cycles
0x11 - 4096 clock cycles
Table 32: LSE oscillator characteristics on page
Doc ID 15962 Rev 6
Option description
79.
STM8L151xx, STM8L152xx