ISP1507CBS STEricsson, ISP1507CBS Datasheet - Page 2

• Manufacturer Part Number: ISP1507CBS
• Manufacturer: STEricsson

Specifications of ISP1507CBS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

1. General description
2. Features
The ISP1507 is a Universal Serial Bus (USB) high-speed host and peripheral transceiver
that is fully compliant with Universal Serial Bus Specification Rev. 2.0 and UTMI+ Low Pin
Interface (ULPI) Specification Rev. 1.1 .
The ISP1507 can transmit and receive USB data at high-speed (480 Mbit/s), full-speed
(12 Mbit/s) and low-speed (1.5 Mbit/s), and provides a pin-optimized, physical layer
front-end attachment to USB host, peripheral and OTG devices.
It is ideal for use in portable electronic devices, such as mobile phones, digital still
cameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audio
players. It allows USB Application-Specific Integrated Circuits (ASICs), Programmable
Logic Devices (PLDs) and any system chip set to interface with the physical layer of the
USB through a 12-pin interface.
The ISP1507 can interface to the link with digital I/O voltages in the range of 1.65 V to
3.6 V.
The ISP1507 is available in HVQFN24 package.
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I
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ISP1507C; ISP1507D
ULPI Hi-Speed Universal Serial Bus host and peripheral
transceiver
Rev. 01 — 28 May 2008
Fully complies with:
Interfaces to host and peripheral cores; optimized for stand-alone and embedded host
applications with an external V
Request Protocol (SRP)-capable peripheral cores
Complete Hi-Speed USB physical front-end solution that supports high-speed
(480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
Supports SRP for reduced power consumption
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N
N
N
N
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N
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Universal Serial Bus Specification Rev. 2.0
UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1
Integrated 45
device pull-up resistor, and 15 k
Integrated parallel-to-serial and serial-to-parallel converters to transmit and receive
USB clock and data recovery to receive USB data up to 500 ppm
Insertion of stuff bits during transmit and discarding of stuff bits during receive
Non-Return-to-Zero Inverted (NRZI) encoding and decoding
Supports bus reset, suspend, resume and high-speed detection handshake (chirp)
Complete control over bus resistors
Data line and V
BUS
10 % high-speed termination resistors, 1.5 k
pulsing session request methods
BUS
supply; stand-alone peripheral cores, and Session
5 % host termination resistors
Product data sheet
5 % full-speed