ISP1507DBS-T NXP Semiconductors, ISP1507DBS-T Datasheet - Page 34

• Manufacturer Part Number: ISP1507DBS-T
• Description: RF Transceiver USB 2.0 ULPI TRNSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1507DBS-T

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant
• Other names: ISP1507DBS,518

NXP Semiconductors
ISP1507C_ISP1507D_1
Product data sheet
9.10.1 Full-speed and low-speed host-initiated suspend and resume
9.10 USB suspend and resume
Figure 14
suspend and sometime later initiates resume signaling to wake up the downstream
peripheral. Note that
LINESTATE updates.
The sequence of events for a host and a peripheral, both with ISP1507, is as follows:
1. Idle: Initially, the host and the peripheral are idle. The host has its 15 k pull-down
2. Suspend: When the peripheral sees no bus activity for 3 ms, it enters the suspend
3. Resume K: When the host wants to wake up the peripheral, it sets OPMODE[1:0] to
4. EOP: When STP is asserted, the ISP1507 on the host side automatically appends an
Fig 13. Preamble sequence
DATA[7:0]
resistors enabled (DP_PULLDOWN and DM_PULLDOWN are set to 1b) and 45
terminations disabled (TERMSELECT is set to 1b). The peripheral has the 1.5 k
pull-up resistor connected to DP for full-speed or DM for low-speed (TERMSELECT is
set to 1b).
state. The peripheral link places the PHY into low-power mode by clearing the
SUSPENDM bit in the FUNC_CTRL register (see
draw only suspend current. The host may or may not be powered down.
10b and transmits a K for at least 20 ms. The peripheral link sees the resume K on
LINESTATE, and asserts STP to wake up the PHY.
EOP of two bits of SE0 at low-speed bit rate, followed by one bit of J. The ISP1507 on
the host side knows to add the EOP because DP_PULLDOWN and DM_PULLDOWN
are set to 1b for a host. After the EOP is completed, the host link sets OPMODE[1:0]
to 00b for normal operation. The peripheral link sees the EOP and also resumes
normal operation.
DP or DM
CLOCK
NXT
STP
DIR
DP and DM timing is not to scale.
illustrates how a host or a hub places a full-speed or low-speed peripheral into
Figure 14
FS SYNC
Rev. 01 — 28 May 2008
TXCMD (low-speed packet ID)
timing is not to scale, and does not show all RXCMD
PRE ID
FS
IDLE (min
4 FS bits)
ULPI HS USB host and peripheral transceiver
ISP1507C; ISP1507D
LS SYNC
Section
D0
LS PID
10.1.2), causing the PHY to
D1
LS D0
© NXP B.V. 2008. All rights reserved.
LS D1
004aaa714
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