SGTL5000XNAA3R2 Freescale, SGTL5000XNAA3R2 Datasheet - Page 23

• Manufacturer Part Number: SGTL5000XNAA3R2
• Manufacturer: Freescale

Specifications of SGTL5000XNAA3R2

• Single Supply Voltage (typ): 1.8/2.5/3.3V
• Lead Free Status / RoHS Status: Compliant

sending the stop condition after two bytes of data, the master
may continue to send data byte pairs for writing, or it may
send extra clocks for reading data byte pairs. In either case,
the access address is incremented after every two bytes of
data. A start or stop condition from the I
the current command. For reads, unless a new address is
written, a new start condition with R/W=0 reads from the
current address and continues to auto increment.
formats. The gray fields are from the I
Table 9. Write Single Location
Table 10. Write Auto increment
Table 11. Read Single Location
Table 12. Read Auto increment
Table 13. Read Continuing Auto increment
SPI
protocol supported by the SGTL5000. The SGTL5000 is
always a slave. The CTRL_AD0_CS is used as the slave
select (SS) when the master wants to select the SGTL5000
for communication. CTRL_CLK is connected to master’s
SCLK and CTRL_DATA is connected to master’s MOSI line.
Analog Integrated Circuit Device Data
Freescale Semiconductor
S
SS
SCK
MOSI
S
S
S
S
The protocol has an auto increment feature. Instead of
The following diagrams describe the different access
Serial Peripheral Interface (SPI) is a communications
Address
Device
Address
Address
Device
Device
Addr
Address
Address
Device
15
Device
31
Addr
14
(0)
W
(0)
W
(0)
W
A
ADDR
byte 1
A
start
A
(0)
W
R
Addr
8
16-bits Register Address
ADDR
byte 1
ADDR
byte 1
start
A
A
Figure 18. Functional Timing Diagram of SPI Protocol
A
2
ADDR
byte 0
Addr
C master, and the
start
7
2
23
C master interrupts
A
Addr
A
byte 1
DATA
[n+2]
ADDR
6
byte 1
A
ADDR
byte 0
ADDR
start
byte 0
Sr
Addr
A
Address
0
A
Device
A
A
byte 1
Sr
DATA
byte 0
DATA
[n+2]
ADDR
byte 0
[n]
Val
(1)
15
white fields are the SGTL5000 responses. Data [n]
corresponds to the data read from the address sent,
data[n+1] is the data from the next register, and so on.
regardless of the VDDIO level.
R
The part only supports allows SPI write operations and does
not support read operations.
communication protocol as supported by SGTL5000 chip.
Note that on the rising edge of the SS, the chip latches to
previous 32 bits of data. It interprets the latest 16-bits as
register value and 16-bits preceding it as register address.
15
S = Start Condition
Sr = Restart Condition
A = Ack
N = Nack
P = Stop Condition
TA2 silicon will allow for up to a 3.6 V I
Figure 18
Address
Val
14
Device
A
A
byte 1
DATA
A
A
[n]
byte 0
DATA
shows the functional timing diagram of the SPI
[n]
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
(1)
Val
R
8
A
byte 1
DATA
[n+3]
byte 1
DATA
16-bits Register Value
byte 0
DATA
A
A
[n]
Val
FUNCTIONAL DEVICE OPERATION
7
byte 1
DATA
[n+1]
byte 1
7
DATA
A
A
Val
A
6
On rising edge of SS, latch
byte 1
the last 32 bits of data
DATA
[n+1]
A
A
byte 0
byte 0
DATA
DATA
[n+3]
2
A
C signal level,
byte 0
Val
DATA
[n+1]
byte 0
DATA
0
0
byte 0
DATA
[n+1]
N
A
SGTL5000
A
N
N
P
P
P
P
P
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