P87LPC762BD NXP Semiconductors, P87LPC762BD Datasheet - Page 32

• Manufacturer Part Number: P87LPC762BD
• Description: MCU 8-Bit 87LP 80C51 CISC 2KB EPROM 5V 20-Pin SO Tube
• Manufacturer: NXP Semiconductors

Specifications of P87LPC762BD

• Package: 20SO
• Device Core: 80C51
• Family Name: 87LP
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 18
• Interface Type: I2C/UART
• Number Of Timers: 2
• Ram Size: 128 Byte
• Program Memory Size: 2 KB
• Program Memory Type: EPROM
• Operating Temperature: 0 to 70 °C

Philips Semiconductors
Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer,
which is an 8-bit Counter with a divide-by-32 prescaler. Figure 24
shows Mode 0 operation.
In this mode, the Timer register is configured as a 13-bit register. As
the count rolls over from all 1s to all 0s, it sets the Timer interrupt
flag TFn. The count input is enabled to the Timer when TRn = 1 and
either GATE = 0 or INTn = 1. (Setting GATE = 1 allows the Timer to
be controlled by external input INTn, to facilitate pulse width
2001 Oct 26
Low power, low price, low pin count (20 pin)
microcontroller with 2 kbyte OTP
TCON
OSC/6
OSC/12
BIT
TCON.7
TCON.6
TCON.5
TCON.4
TCON.3
TCON.2
TCON.1
TCON.0
INTn PIN
Tn PIN
GATE
TRn
Address: 88h
Bit Addressable
OR
SYMBOL
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
TF1
7
FUNCTION
Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the
interrupt is processed, or by software.
Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter 1 on/off.
Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the
processor vectors to the interrupt routine, or by software.
Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0 on/off.
Interrupt 1 Edge flag. Set by hardware when external interrupt 1 edge is detected. Cleared by
hardware when the interrupt is processed, or by software.
Interrupt 1 Type control bit. Set/cleared by software to specify falling edge/low level triggered
external interrupts.
Interrupt 0 Edge flag. Set by hardware when external interrupt 0 edge is detected. Cleared by
hardware when the interrupt is processed, or by software.
Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level triggered
external interrupts.
C/T = 1
Figure 24. Timer/Counter 0 or 1 in Mode 0 (13-Bit Counter)
C/T = 0
TR1
Figure 23. Timer/Counter Control Register (TCON)
6
TF0
5
CONTROL
TR0
4
29
IE1
3
measurements). TRn is a control bit in the Special Function Register
TCON (Figure 23). The GATE bit is in the TMOD register.
The 13-bit register consists of all 8 bits of THn and the lower 5 bits
of TLn. The upper 3 bits of TLn are indeterminate and should be
ignored. Setting the run flag (TRn) does not clear the registers.
Mode 0 operation is the same for Timer 0 and Timer 1. See
Figure 24. There are two different GATE bits, one for Timer 1
(TMOD.7) and one for Timer 0 (TMOD.3).
(5 BITS)
TLn
IT1
2
(8 BITS)
IE0
THn
1
TOGGLE
OVERFLOW
IT0
0
TnOE
TFn
87LPC762
Reset Value: 00h
SU01172
INTERRUPT
Preliminary data
Tn PIN
SU01173