M36L0T7050B0ZAQF STMicroelectronics, M36L0T7050B0ZAQF Datasheet

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M36L0T7050B0ZAQF

Manufacturer Part Number
M36L0T7050B0ZAQF
Description
Manufacturer
STMicroelectronics
Datasheet

Specifications of M36L0T7050B0ZAQF

Operating Supply Voltage (max)
3.3V
Operating Temperature (max)
85C
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
FEATURES SUMMARY
FLASH MEMORY
December 2004
MULTI-CHIP PACKAGE
SUPPLY VOLTAGE
ELECTRONIC SIGNATURE
PACKAGE
SYNCHRONOUS / ASYNCHRONOUS READ
SYNCHRONOUS BURST READ SUSPEND
PROGRAMMING TIME
MEMORY ORGANIZATION
DUAL OPERATIONS
SECURITY
1 die of 128Mbit (8Mx16, Multiple Bank,
Multi-level, Burst) Flash Memory
1 die of 32Mbit (2Mx16) Pseudo SRAM
V
V
V
Manufacturer Code: 20h
Device Code (Top Flash Configuration)
M36L0T7050T0: 88C4h
Device Code (Bottom Flash
Configuration) M36L0T7050B0: 88C5h
Compliant with Lead-Free Soldering
Processes
Lead-Free Versions
Synchronous Burst Read mode: 50MHz
Asynchronous Page Read mode
Random Access: 90ns
10µs typical Word program time using
Write to Buffer and Program
Multiple Bank Memory Array: 8 Mbit
Banks
Parameter Blocks (Top or Bottom
location)
program/erase in one Bank while read in
others
No delay between read and write
operations
64 bit unique device number
2112 bit user programmable OTP Cells
DDF
DDP
PP
128Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory
= 9V for fast program (12V tolerant)
= 1.7 to 2V
= V
DDQ
= 2.7 to 3.3V
32Mbit (2M x16) PSRAM, Multi-Chip Package
Figure 1. Package
PSRAM
– Deep Power-Down
– 4 Mbit Partial Array Refresh
– 8 Mbit Partial Array Refresh
– 16 Mbit Partial Array Refresh
BLOCK LOCKING
COMMON FLASH INTERFACE (CFI)
100,000 PROGRAM/ERASE CYCLES per
BLOCK
ACCESS TIME: 70ns
LOW STANDBY CURRENT: 100µA
DEEP POWER-DOWN CURRENT: 10µA
BYTE CONTROL: UB
PROGRAMMABLE PARTIAL ARRAY
8 WORD PAGE ACCESS CAPABILITY: 18ns
POWER-DOWN MODES
All blocks locked at power-up
Any combination of blocks can be locked
with zero latency
WP for Block Lock-Down
Absolute Write Protection with V
M36L0T7050B0
TFBGA88 (ZAQ)
M36L0T7050T0
8 x 10mm
FBGA
P
/LB
P
PP
= V
1/18
SS

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M36L0T7050B0ZAQF Summary of contents

Page 1

Bank, Multi-Level, Burst) Flash Memory FEATURES SUMMARY MULTI-CHIP PACKAGE – 1 die of 128Mbit (8Mx16, Multiple Bank, Multi-level, Burst) Flash Memory – 1 die of 32Mbit (2Mx16) Pseudo SRAM SUPPLY VOLTAGE – 1 DDF ...

Page 2

M36L0T7050T0, M36L0T7050B0 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

Table 4. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

M36L0T7050T0, M36L0T7050B0 SUMMARY DESCRIPTION The M36L0T7050T0 and M36L0T7050B0 com- bine two memory devices in a Multi-Chip Package: a 128-Mbit, Multiple Bank Flash memory, the M30L0T7000T0 or M30L0T7000B0, and a 32-Mbit PseudoSRAM, the M69AW048B. Recommended operating conditions do not allow more ...

Page 5

Figure 3. TFBGA Connections (Top view through package ...

Page 6

M36L0T7050T0, M36L0T7050B0 SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram Names, for a brief overview of the signals connect this device. Address Inputs (A0-A22). Addresses are common inputs for the Flash Memory and the PSRAM components. The other lines ...

Page 7

I/O data bus. Write Enable (W ). The Write Enable trols the Bus Write operation of the memory. Upper Byte Enable (UB ). The Upper Byte En- P ...

Page 8

M36L0T7050T0, M36L0T7050B0 FUNCTIONAL DESCRIPTION The PSRAM and Flash memory components have separate power supplies but share the same grounds. They are distinguished by three Chip En- able inputs: E for the Flash memory and for the PSRAM. ...

Page 9

Table 2. Main Operating Modes Operation Flash Read Flash Write Flash Address Latch Flash Output ...

Page 10

... PAR 8Mb PAR 16Mb PAR 10/18 M30L0T7000(T/B)0 datasheet which is available from your local STMicroelectronics distributor. see the device, see the M69AW048B datasheet which is available from the internet site http://www.st.com Ta- or from your local STMicroelectronics distributor. Power-Down Configuration Data DQ8-DQ2 ...

Page 11

... Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn- assembly), the ST ECOPACK and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. plied. Exposure to Absolute Maximum Rating con- ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. Parameter ...

Page 12

M36L0T7050T0, M36L0T7050B0 DC AND AC PARAMETERS This section summarizes the operating measure- ment conditions, and the DC and AC characteris- tics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed ...

Page 13

Table 7. Flash DC Characteristics - Currents Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO Supply Current Asynchronous Read (f=6MHz) Supply Current Synchronous Read (f=40MHz) I DD1 Supply Current Synchronous Read (f=50MHz) Supply Current I DD2 ...

Page 14

M36L0T7050T0, M36L0T7050B0 Table 8. Flash Memory DC Characteristics - Voltages Symbol Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage Program Voltage-Logic PP1 PPF V V ...

Page 15

PACKAGE MECHANICAL Figure 7. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Bottom View Outline BALL "A1" FE FE1 Note: Drawing is not to scale. Table 10. Stacked TFBGA88 8x10mm - 8x10 active ball ...

Page 16

M36L0T7050T0, M36L0T7050B0 PART NUMBERING Table 11. Ordering Information Scheme Example: Device Type M36 = Multi-Chip Package (Flash + RAM) Flash 1 Architecture L = Multilevel, Multiple Bank, Burst mode Flash 2 Architecture Die Operating Voltage T = ...

Page 17

REVISION HISTORY Table 12. Document Revision History Date Version 29-Jul-2003 0.1 First Issue Document status promoted from Target Specification to full Datasheet. TFBGA88 package specifications updated, package fully compliant with the ST 10-Dec-2004 1.0 ECOPACK specification. Flash memory and PSRAM ...

Page 18

... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...

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