MT47H128M16RT-25E:C Micron Technology Inc, MT47H128M16RT-25E:C Datasheet - Page 122

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MT47H128M16RT-25E:C

Manufacturer Part Number
MT47H128M16RT-25E:C
Description
DRAM Chip DDR2 SDRAM 2G-Bit 128Mx16 1.8V 84-Pin FBGA Tray
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Series
-r
Datasheet

Specifications of MT47H128M16RT-25E:C

Package
84FBGA
Density
2 Gb
Address Bus Width
17 Bit
Operating Supply Voltage
1.8 V
Maximum Clock Rate
800 MHz
Maximum Random Access Time
0.4 ns
Operating Temperature
0 to 70 °C
Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
2G (128M x 16)
Speed
2.5ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Package / Case
84-TFBGA
Lead Free Status / RoHS Status
Compliant

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Figure 73: WRITE-to-Power-Down or Self Refresh Entry
Figure 74: WRITE with Auto Precharge-to-Power-Down or Self Refresh Entry
PDF: 09005aef824f87b6
2gbddr2.pdf – Rev. E 06/10 EN
DQS, DQS#
DQS, DQS#
Command
Command
Address
Address
CK#
CKE
A10
CK#
CKE
A10
DQ
DQ
CK
CK
WRITE
Valid
Valid
WRITE
T0
T0
Notes:
Note:
NOP
NOP
T1
T1
WL = 3
WL = 3
1. Power-down or self refresh entry may occur after the WRITE burst completes.
1. Internal PRECHARGE occurs at Ta0 when WR has completed; power-down entry may oc-
2. WR is programmed through MR9–MR11 and represents (
cur 1 x
to next integer
NOP
NOP
T2
T2
t
CK later at Ta1, prior to
NOP
t
DO
NOP
DO
CK.
T3
T3
DO
DO
122
Valid
Valid
DO
DO
T4
T4
t
RP being satisfied.
DO
DO
Indicates a break in
time scale
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Valid
Valid
T5
T5
2Gb: x4, x8, x16 DDR2 SDRAM
WR 2
Valid 1
Valid
t WTR
Ta0
T6
Transitioning Data
t
self refresh entry 1
self refresh entry
Power-down or
WR [MIN] ns/
Power-down or
Transitioning Data
Power-Down Mode
© 2006 Micron Technology, Inc. All rights reserved.
NOP 1
NOP
Ta1
T7
t
CK) rounded up
t CKE (MIN)
t CKE (MIN)
Ta2
T8
Don’t Care
Don’t Care

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