MT49H32M9BM-25 Micron Technology Inc, MT49H32M9BM-25 Datasheet - Page 59

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MT49H32M9BM-25

Manufacturer Part Number
MT49H32M9BM-25
Description
Manufacturer
Micron Technology Inc
Type
RLDRAMr
Datasheet

Specifications of MT49H32M9BM-25

Organization
32Mx9
Density
288Mb
Address Bus
22b
Maximum Clock Rate
400MHz
Operating Supply Voltage (typ)
1.8V
Package Type
uBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
779mA
Pin Count
144
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT49H32M9BM-25
Manufacturer:
MICRON/美光
Quantity:
20 000
Part Number:
MT49H32M9BM-25:B
Manufacturer:
MICRON/美光
Quantity:
20 000
Company:
Part Number:
MT49H32M9BM-25:B
Quantity:
260
Figure 36:
PDF: 09005aef80a41b59/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev B 5/08 EN
COMMAND
ADDRESS
ADDRESS
BANK
V
V
V
DK#
DQ
DD
REF
CK#
V
DM
V
DK
R
CK
EXT
DD
TT
Q
TT
High-Z
NOP
T0
Power-Up/Initialization Sequence in Multiplexed Address Mode
t CKH
t DKH
Power-up:
V
clock (CK, CK#)
DD
t CK
t DK
and stable
Notes:
T = 200µs (MIN)
t CKL
t DKL
NOP
T1
1. Recommended that all address pins held LOW during dummy MRS commands.
2. A10–A18 must be LOW.
3. Set address A5 HIGH. This enbles the part to enter multiplexed address mode when in non-
4. Address A5 must be set HIGH. This and the following step set the desired mode register
5. Any command or address.
6. The above sequence must be followed in order to power up the RLDRAM in the multiplexed
7. DLL must be reset if
8. CK and CK# must separated at all times to prevent bogus commands from being issued.
9. The sequence of the eight AUTO REFRESH commands (with respect to the 1,024 NOP com-
multiplexed mode operation. Multiplexed address mode can also be entered at some later
time by issuing an MRS command with A5 HIGH. Once address bit A5 is set HIGH,
must be satisfied before the two-cycle multiplexed mode MRS command is issued.
once the RLDRAM is in multiplexed address mode.
address mode.
mands) does not matter. As is required for any operation,
AUTO REFRESH command and a subsequent VALID command to the same bank.
NOP
T2
288Mb: x9, x18, x36 2.5V V
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NOP
T3
CODE
MRS
T4
1,2
t
CK or V
CODE
MRS
T5
DD
58
1,2
are changed.
CODE
MRS
T6
2,3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t MRSC
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Ax
T7
, 1.8V V
MRS
2,4
NOP
Ay
T8
2
DD
t
t MRSC
RC must be met between an
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, HSTL, CIO, RLDRAM II
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Bank 0
©2003 Micron Technology, Inc. All rights reserved.
T9
REF
all banks 9
Refresh
Indicates a break in
time scale
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Bank 7
REF
T10
Operations
1,024 NOP
commands
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DON’T CARE
t
VALID
VALID
VALID
MRSC
T11
5
5
5

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