MT48LC16M4A2TG-7EL Micron Technology Inc, MT48LC16M4A2TG-7EL Datasheet - Page 36

• Manufacturer Part Number: MT48LC16M4A2TG-7EL
• Manufacturer: Micron Technology Inc

Specifications of MT48LC16M4A2TG-7EL

• Lead Free Status / RoHS Status: Not Compliant

Figure 27:
Figure 28:
Concurrent Auto Precharge
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
Clock Suspend During WRITE Burst
Clock Suspend During READ Burst
Note:
COMMAND
COMMAND
An access command (READ or WRITE) to another bank while an access command with
auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM
supports concurrent auto precharge. Micron SDRAMs support concurrent auto
precharge. Four cases where concurrent auto precharge occurs are defined below.
INTERNAL
INTERNAL
ADDRESS
ADDRESS
CLOCK
CLOCK
For this example, CL = 2, BL = 4 or greater, and DQM is LOW.
CLK
CKE
CLK
CKE
D
DQ
IN
NOP
T0
BANK,
COL n
T0
READ
WRITE
BANK,
COL n
T1
T1
D
NOP
n
IN
TRANSITIONING DATA
T2
T2
NOP
36
D
OUT
n
TRANSITIONING DATA
T3
T3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
n + 1
D
OUT
NOP
n + 1
T4
T4
D
NOP
IN
DON’T CARE
T5
T5
NOP
n + 2
D
NOP
IN
n + 2
D
OUT
64Mb: x4, x8, x16 SDRAM
DON’T CARE
T6
NOP
D
n + 3
OUT
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Commands