MT48LC16M4A2TG-7EL Micron Technology Inc, MT48LC16M4A2TG-7EL Datasheet - Page 66

• Manufacturer Part Number: MT48LC16M4A2TG-7EL
• Manufacturer: Micron Technology Inc

Specifications of MT48LC16M4A2TG-7EL

• Lead Free Status / RoHS Status: Not Compliant

Figure 49:
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
DQML, DQMH
COMMAND
A0–A9, A11
BA0, BA1
DQM /
CLK
CKE
A10
DQ
t CMS
t CKS
Single WRITE – Without Auto Precharge
t AS
t AS
t AS
ACTIVE
T0
ROW
ROW
BANK
t CKH
t CMH
Notes:
t AH
t AH
t AH
t RCD
t RAS
t RC
t CK
T1
1. For this example, BL = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 15ns is required between <D
3. x16: A8, A9 and A11 = “Don’t Care”
4. PRECHARGE command not allowed or
NOP
DISABLE AUTO PRECHARGE
frequency.
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
t CMS
t CL
COLUMN m 3
t DS
WRITE
BANK
D
T2
IN
t CMH
t CH
t DH
m
t WR
2
NOP 4
T3
66
IN
m> and the PRECHARGE command, regardless of
NOP 4
T4
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RAS would be violated.
SINGLE BANK
PRECHARGE
ALL BANKS
BANK
T5
T6
NOP
t RP
64Mb: x4, x8, x16 SDRAM
©2000 Micron Technology, Inc. All rights reserved.
BANK
ACTIVE
ROW
T7
Timing Diagrams
T8
NOP
DON’T CARE