M25PE80-VMN6P NUMONYX, M25PE80-VMN6P Datasheet - Page 13

• Manufacturer Part Number: M25PE80-VMN6P
• Description: Flash Mem Serial-SPI 3.3V 8M-Bit 1M x 8 8ns 8-Pin SOIC N Tray
• Manufacturer: NUMONYX

Specifications of M25PE80-VMN6P

• Package: 8SOIC N
• Cell Type: NOR
• Density: 8 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 256Byte x 4096
• Timing Type: Synchronous
• Operating Temperature: -40 to 85 °C
• Interface Type: Serial-SPI
• Lead Free Status / RoHS Status: Compliant

M25PE80
4.3
4.4
4.5
4.6
A fast way to modify data
The page program (PP) instruction provides a fast way of modifying data (up to 256
contiguous bytes at a time), provided that it only involves resetting bits to 0 that had
previously been set to 1.
This might be:
For optimized timings, it is recommended to use the page program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several page
program (PP) sequences with each containing only a few bytes (see
program
operation, T9HX (0.11 µm)
Polling during a write, program or erase cycle
A further improvement in the write, program or erase time can be achieved by not waiting for
the worst case delay (t
provided in the status register so that the application program can monitor its value, polling it
to establish when the previous cycle is complete.
Reset
An internal power-on reset circuit helps protect against inadvertent data writes. Addition
protection is provided by driving Reset (Reset) Low during the power-on process, and only
driving it High when V
Active power, standby power and deep power-down modes
When Chip Select (S) is Low, the device is selected, and in the active power mode.
When Chip Select (S) is High, the device is deselected, but could remain in the active power
mode until all internal cycles have completed (program, erase, write). The device then goes
in to the standby power mode. The device consumption drops to I
The deep power-down mode is entered when the specific instruction (the deep power-down
(DP) instruction) is executed. The device consumption drops further to I
mode, only the release from deep power-down instruction is accepted. All other instructions
are ignored. The device remains in the deep power-down mode until the release from deep
power-down instruction is executed. This can be used as an extra software protection
mechanism, when the device is not in active use, to protect the device from inadvertent
write, program or erase instructions.
when the designer is programming the device for the first time
when the designer knows that the page has already been erased by an earlier page
erase (PE), subsector erase (SSE), sector erase (SE) or bulk erase (BE) instruction.
This is useful, for example, when storing a fast stream of data, having first performed
the erase cycle when time was available
when the designer knows that the only changes involve resetting bits to ‘0’ that are still
set to ‘1’. When this method is possible, it has the additional advantage of minimizing
the number of unnecessary erase operations, and the extra stress incurred by each
page
(PP),
Table 22: AC
CC
PW
has reached the correct voltage level, V
, t
PP
process)).
characteristics, and
, t
PE
, t
SSE
, t
SE
or t
BE
Table 24: AC characteristics (75 MHz
). The write in progress (WIP) bit is
CC
CC1
(min).
Section 6.10: Page
.
Operating features
CC2
. When in this
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