M25PE80-VMN6P NUMONYX, M25PE80-VMN6P Datasheet - Page 35

• Manufacturer Part Number: M25PE80-VMN6P
• Description: Flash Mem Serial-SPI 3.3V 8M-Bit 1M x 8 8ns 8-Pin SOIC N Tray
• Manufacturer: NUMONYX

Specifications of M25PE80-VMN6P

• Package: 8SOIC N
• Cell Type: NOR
• Density: 8 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 256Byte x 4096
• Timing Type: Synchronous
• Operating Temperature: -40 to 85 °C
• Interface Type: Serial-SPI
• Lead Free Status / RoHS Status: Compliant

M25PE80
6.10
Page program (PP)
The page program (PP) instruction allows bytes to be programmed in the memory (changing
bits from 1 to 0, only). Before it can be accepted, a write enable (WREN) instruction must
previously have been executed. After the write enable (WREN) instruction has been
decoded, the device sets the write enable latch (WEL).
The page program (PP) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, three address bytes and at least one data byte on serial data input (D). If
the 8 least significant address bits (A7-A0) are not all zero, all transmitted data exceeding
the addressed page boundary roll over, and are programmed from the start address of the
same page (the one whose 8 least significant address bits (A7-A0) are all zero). Chip Select
(S) must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in
If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less
than 256 data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the page program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several page
program (PP) sequences with each containing only a few bytes (see
characteristics
process)).
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the page program (PP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed page program cycle (whose
duration is t
may be read to check the value of the write in progress (WIP) bit. The write in progress
(WIP) bit is 1 during the self-timed page program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is complete, the write enable latch (WEL) bit is reset.
A page program (PP) instruction applied to a page that is hardware or software protected is
not executed.
Any page program (PP) instruction, while an erase, program or write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
If Reset (Reset) is driven Low while a page program (PP) cycle is in progress, the page
program cycle is interrupted and the programmed data may be corrupted (see
Device status after a Reset Low
mode and a time of t
Chip Select (S) Low. For the value of t
Section 11: DC and AC
PP
) is initiated. While the page program cycle is in progress, the status register
and
Table 24: AC characteristics (75 MHz operation, T9HX (0.11 µm)
RHSL
parameters.
is then required before the device can be re-selected by driving
pulse). On Reset going Low, the device enters the reset
RHSL
Figure
see
16.
Table 26: Timings after a Reset Low pulse
Table 22: AC
Table 15:
Instructions
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in