MT29F2G16ABAEAWP-IT:E Micron Technology Inc, MT29F2G16ABAEAWP-IT:E Datasheet - Page 102

• Manufacturer Part Number: MT29F2G16ABAEAWP-IT:E
• Description: MICMT29F2G16ABAEAWP-IT:E 2G SLC NAND FLA
• Manufacturer: Micron Technology Inc

Specifications of MT29F2G16ABAEAWP-IT:E

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Internal ECC and Spare Area Mapping for ECC
Figure 78: Spare Area Mapping (x8)
PDF: 09005aef83b83f42
m69a_2gb_nand.pdf – Rev. H 09/10 EN
Max Byte Min Byte
Address
1FFh
3FFh
5FFh
7FFh
801h
803h
807h
80Fh
811h
813h
817h
81Fh
821h
823h
827h
82Fh
831h
833h
837h
83Fh
Address
000h
200h
400h
600h
800h
802h
804h
808h
810h
812h
814h
818h
820h
822h
824h
828h
830h
832h
834h
838h
Internal ECC enables 5-bit detection and 4-bit error correction in 512 bytes (x8) or 256
words (x16) of the main area and 4 bytes (x8) or 2 words (x16) of metadata I in the spare
area. The metadata II area, which consists of two bytes (x8) and one word (x16), is not
ECC protected. During the busy time for PROGRAM operations, internal ECC generates
parity bits when error detection is complete.
During READ operations the device executes the internal ECC engine (5-bit detection
and 4-bit error correction). When the READ operaton is complete, read status bit 0
must be checked to determine whether errors larger than four bits have occurred.
Following the READ STATUS command, the device must be returned to read mode by
issuing the 00h command.
Limitations of internal ECC include the spare area, defined in the figures below, and
ECC parity areas that cannot be written to. Each ECC user area (referred to as main and
spare) must be written within one partial-page program so that the NAND device can
calculate the proper ECC parity. The number of partial-page programs within a page
cannot exceed four.
ECC Protected
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
Spare 0 User metadata I
Spare 0 ECC for main/spare 0
Spare 1 User metadata I
Spare 1 ECC for main/spare 1
Spare 2 User metadata I
Spare 2 ECC for main/spare 2
Spare 3 User metadata I
Spare 3 ECC for main/spare 3
Main 0 User data
Main 1 User data
Main 2 User data
Main 3 User data
Area
Description
Reserved
User metadata II
Reserved
User metadata II
Reserved
User metadata II
User data
User metadata II
Internal ECC and Spare Area Mapping for ECC
102
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2Gb: x8, x16 NAND Flash Memory
Information
Bad Block
2 bytes
8 bytes
Parity
© 2009 Micron Technology, Inc. All rights reserved.
ECC
(Metadata)
User Data
6 bytes