MT45W4MW16PCGA-70 IT Micron Technology Inc, MT45W4MW16PCGA-70 IT Datasheet
MT45W4MW16PCGA-70 IT
Specifications of MT45W4MW16PCGA-70 IT
Related parts for MT45W4MW16PCGA-70 IT
MT45W4MW16PCGA-70 IT Summary of contents
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... A5 A6 DQ1 DQ2 DQ11 A17 DQ3 DQ12 A21 A16 DQ4 DQ14 A14 A15 DQ5 DQ6 DQ13 G DQ15 A19 A12 A13 WE# DQ7 H A18 A9 A10 A11 A20 A8 Top View (Ball Down) Part Number Example: MT45W4MW16PCGA-70LWT ©2005 Micron Technology, Inc. All rights reserved. Features ...
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... General Description Micron oped for low-power, portable applications. The MT45W4MW16PCGA is a 64Mb DRAM core device, organized as 4 Meg x 16 bits. This device includes an industry-standard asynchronous memory interface found on other low-power SRAM or PSRAM offerings. For seamless operation on an asynchronous memory bus, CellularRAM products incor- porate a transparent self-refresh mechanism ...
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Table 1: VFBGA Ball Descriptions VFBGA Assignment Symbol Type E3, H6, G2, H1, A[21:0] Input D3, E4, F4, F3, G4, G3, H5, H4, H3, H2, D4, C4, C3, B4, B3, A5, A4 ZZ# Input B5 CE# Input A2 ...
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Part Numbering Information Micron CellularRAM devices are available in several different configurations and densi- ties (see Figure 3). Figure 3: Part Number Chart Micron Technology Product Family 45 = PSRAM/CellularRAM Memory Operating Core Voltage ...
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... Functional Description In general, the MT45W4MW16PCGA device is a high-density alternative to SRAM and pseudo-SRAM products, popular in low-power, portable applications. The MT45W4MW16PCGA contains a 67,108,864-bit DRAM core, organized as 4,194,304 addresses by 16 bits. This device implements the industry-standard, asynchronous memory interface found on other low-power SRAM or PSRAM offerings. Page mode accesses are also included as a bandwidth-enhancing extension to the asynchronous read protocol ...
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Figure 5: READ Operation CE# OE# WE# ADDRESS DATA LB#/UB# Figure 6: WRITE Operation CE# OE# WE# ADDRESS DATA LB#/UB# PDF: 09005aef81f0698d / Source: 09005aef81f06935 64mb_asyncpage_cr1_0_p25z.fm - Rev. D 7/09 EN 64Mb: 4 Meg x 16 Async/Page CellularRAM 1.0 Address ...
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Page Mode READ Operation Page mode is a performance-enhancing extension to the legacy asynchronous READ operation. In page-mode-capable products, after an initial asynchronous read access is performed, adjacent addresses can be read quickly by simply changing the low-order address. Addresses ...
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Low-Power Operation Standby Mode Operation During standby, the device current consumption is reduced to the level necessary to perform the DRAM refresh operation. Standby operation occurs when CE# and ZZ# are HIGH. The device will enter a reduced power state ...
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Figure 8: Software Access PAR Functionality NO Deep Power-Down Operation (DPD) DPD operation disables all refresh-related activity. This mode is used when the system does not require the storage provided by the CellularRAM device. Any stored data will become corrupted ...
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Device Registers There are two registers on this device: the configuration register (CR) and the device ID register (DIDR). Configuration Register (CR) Operation The CR defines how the CellularRAM device performs its transparent self refresh. Altering the refresh parameters can ...
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Sleep Mode (CR[4]) Default = PAR Enabled The sleep mode bit determines which low-power mode entered when ZZ# is driven LOW. If CR[ PAR operation is enabled. If CR[ DPD operation is enabled. ...
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Software Access to the Configuration Register The contents of the CR can be read and modified using a software sequence. The nature of this access mechanism may eliminate the need for the ZZ# ball. If the software mechanism is used, ...
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Figure 12: Software Access Read Configuration Register Address CE# OE# WE# LB#/UB# Data PDF: 09005aef81f0698d / Source: 09005aef81f06935 64mb_asyncpage_cr1_0_p25z.fm - Rev. D 7/09 EN 64Mb: 4 Meg x 16 Async/Page CellularRAM 1.0 READ READ WRITE Address Address Address (MAX) (MAX) ...
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Electrical Characteristics Stresses greater than those listed in Table 5 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the ...
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Table 7: Operating Conditions Wireless temperature (–30ºC < T Operating Current Asynchronous random READ/WRITE Asynchronous page READ Standby current Notes –30°C exceeds CellularRAM Workgroup 1.0 specification of –25°C. 2. This parameter is specified with the outputs disabled ...
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Figure 13: Typical Refresh Current vs. Temperature ( –40 –30 –20 –10 0 Table 9: Deep Power-Down Specifications Description Deep power-down Notes: 1. Typical (TYP) I Table 10: Capacitance Description Input ...
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Timing Requirements Table 11: Asynchronous READ Cycle Timing Requirements Parameter Address access time Page access time LB#/UB# access time LB#/UB# disable to DQ High-Z output LB#/UB# enable to Low-Z output Maximum CE# pulse width Chip select access time Chip disable ...
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Table 12: Asynchronous WRITE Cycle Timing Requirements Parameter Address and ADV# LOW setup time Address valid to end of WRITE LB#/UB# select to end of WRITE CE# HIGH time during WRITEs between subsequent async operations Chip enable to end of ...
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Timing Diagrams Figure 16: Initialization Period 1. Figure 17: DPD Entry and Exit Timing CE# Write DPD enabled RCR[ Table 13: Initialization Timing Parameters Parameter Time from DPD entry to DPD ...
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Figure 18: Load Configuration Register Address CE# LB#/UB# WE# OE# ZZ# Figure 19: Asynchronous READ (WE A[21:0] CE# LB#/UB# OE# WE# DQ[15:0] PDF: 09005aef81f0698d / Source: 09005aef81f06935 64mb_asyncpage_cr1_0_p25z.fm - Rev. D 7/09 EN 64Mb: 4 Meg x 16 ...
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Figure 20: Page Mode READ (WE A[21:4] A[3:0] CE# LB#/UB# OE# WE# DQ[15:0] Figure 21: CE#-Controlled Asynchronous WRITE A[21:0] LB#/UB# OE# WE# DQ[15:0] DQ[15:0] OUT PDF: 09005aef81f0698d / Source: 09005aef81f06935 64mb_asyncpage_cr1_0_p25z.fm - Rev. D 7/09 EN 64Mb: 4 ...
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Figure 22: LB#/UB#-Controlled Asynchronous WRITE A[21:0] CE# LB#/UB# OE# WE# DQ[15:0] DQ[15:0] OUT Figure 23: WE#-Controlled Asynchronous WRITE A[21:0] CE# LB#/UB# OE# WE# DQ[15:0] DQ[15:0 OUT PDF: 09005aef81f0698d / Source: 09005aef81f06935 64mb_asyncpage_cr1_0_p25z.fm - Rev. D 7/09 EN 64Mb: 4 Meg ...
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... All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. The MT45W4MW16PCGA uses “green” packaging. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners ...