MT45W4MW16PCGA-70 IT Micron Technology Inc, MT45W4MW16PCGA-70 IT Datasheet - Page 5

• Manufacturer Part Number: MT45W4MW16PCGA-70 IT
• Manufacturer: Micron Technology Inc

Specifications of MT45W4MW16PCGA-70 IT

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Functional Description
Power-Up Initialization
Figure 4:
Bus Operating Modes
Asynchronous Mode
PDF: 09005aef81f0698d / Source: 09005aef81f06935
64mb_asyncpage_cr1_0_p25z.fm - Rev. D 7/09 EN
Power-Up Initialization Timing
In general, the MT45W4MW16PCGA device is a high-density alternative to SRAM and
pseudo-SRAM products, popular in low-power, portable applications.
The MT45W4MW16PCGA contains a 67,108,864-bit DRAM core, organized as 4,194,304
addresses by 16 bits. This device implements the industry-standard, asynchronous
memory interface found on other low-power SRAM or PSRAM offerings. Page mode
accesses are also included as a bandwidth-enhancing extension to the asynchronous
read protocol.
CellularRAM products include an on-chip voltage sensor used to launch the power-up
initialization process. Initialization will configure the register with the default settings.
V
above 1.7V, the device will require 150µs to complete its self-initialization process.
During the initialization period, CE# should remain HIGH. When initialization is
complete, the device is ready for normal operation.
V
The MT45W4MW16PCGA CellularRAM product incorporates the industry-standard
asynchronous interface found on other low-power SRAM or PSRAM offerings. This bus
interface supports asynchronous READ and WRITE transfers as well as bandwidth-
enhancing page mode READ operations. The specific interface supported is defined by
the value loaded into the CR.
CellularRAM products power up in the asynchronous operating mode. This mode uses
the industry-standard SRAM control bus (CE#, OE#, WE#, LB#/UB#). READ operations
(Figure 5 on page 6) are initiated by bringing CE#, OE#, and LB#/UB# LOW while
keeping WE# HIGH. Valid data will be driven out of the I/Os after the specified access
time has elapsed. WRITE operations (Figure 6 on page 6) occur when CE#, WE#, and
LB#/UB# are driven LOW. During asynchronous WRITE operations, the OE# level is a
“Don’t Care,” and WE# will override OE#. The data to be written is latched on the rising
edge of CE#, WE#, or LB#/UB# (whichever occurs first). WE# LOW time must be limited
to
CC
CC
V
CC
t
Q
CEM.
and V
V
CC
= 1.7V
CC
Q must be applied simultaneously. When they reach a stable level at or
Device initialization
t
PU > 150µs
64Mb: 4 Meg x 16 Async/Page CellularRAM 1.0
5
Device ready for
normal operation
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Functional Description
©2005 Micron Technology, Inc. All rights reserved.