MT8LSDT3264HY-133D2 Micron Technology Inc, MT8LSDT3264HY-133D2 Datasheet - Page 8

• Manufacturer Part Number: MT8LSDT3264HY-133D2
• Description: MODULE SDRAM 256MB 144SODIMM
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT8LSDT3264HY-133D2

• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 144SODIMM
• Device Core Size: 64b
• Organization: 32Mx64
• Total Density: 256MByte
• Chip Density: 256Mb
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 548mA
• Number Of Elements: 8
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 144
• Mounting: Socket
• Memory Type: SDRAM
• Memory Size: 256MB
• Speed: 133MHz
• Features: -
• Package / Case: 144-SODIMM
• Lead Free Status / RoHS Status: Compliant

Table 7:
09005aef8077d63a
SD8C8_16_32x64HG.fm - Rev. C 6/04 EN
NOTE:
LENGTH
1. For full-page accesses: y = 256 (64MB), y= 512 (128MB
2. For a burst length of two, A1–Ai select the block-of-
3. For a burst length of four, A2–Ai select the block-of-
4. For a burst length of eight, A3–Ai select the block-of-
5. For a full-page burst, the full row is selected and A0–Ai
6. Whenever a boundary of the block is reached within a
7. For a burst length of one, A0–Ai select the unique col-
8. i = 7 for 64MB modules
BURST
Page
Full
(y)
and 256MB)
two burst; A0 selects the starting column within the
block.
four burst; A0–A1 select the starting column within
the block.
eight burst; A0–A2 select the starting column within
the block.
select the starting column.
given sequence above, the following access wraps
within the block.
umn to be accessed, and mode register bit M3 is
ignored.
i = 8 for 128MB and 256MB modules
2
4
8
(location 0-y)
A2 A1 A0
STARTING
ADDRESS
0
0
0
0
1
1
1
1
COLUMN
n = i
Burst Definition Table
A1 A0
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ORDER OF ACCESSES WITHIN A
Cn + 3, Cn + 4...
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
SEQUENTIAL
Cn, Cn + 1,
…Cn - 1,
TYPE =
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
Cn + 2
Cn…
0-1
1-0
BURST
INTERLEAVED
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not supported
TYPE =
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0
8
CAS Latency
between the registration of a READ command and the
availability of the first piece of output data. The latency
can be set to two or three clocks.
and the latency is m clocks, the data will be available
by clock edge n + m. The DQ will start driving as a
result of the clock edge one cycle earlier (n + m - 1),
and, provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example,
assuming that the clock cycle time is such that all rele-
vant access times are met, if a READ command is regis-
tered at T0 and the latency is programmed to two
clocks, the DQ will start driving after T1 and the data
will be valid by T2, as shown in Figure 5, CAS Latency
Diagram. Table 8, CAS Latency Table, on page 9 indi-
cates the operating frequencies at which each CAS
latency setting can be used.
known operation or incompatibility with future ver-
sions may result.
Operating Mode
M7 and M8 to zero; the other combinations of values
for M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
READ and WRITE bursts.
COMMAND
COMMAND
64MB, 128MB, 256MB (x64, DR)
The CAS latency is the delay, in clock cycles,
If a READ command is registered at clock edge n,
Reserved states should not be used, because un-
The normal operating mode is selected by setting
CLK
CLK
DQ
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Figure 5: CAS Latency Diagram
READ
144-PIN SDRAM SODIMM
READ
T0
T0
CAS Latency = 2
NOP
NOP
T1
T1
t
t AC
LZ
CAS Latency = 3
©2004 Micron Technology, Inc. All rights reserved.
T2
NOP
T2
NOP
t
t AC
LZ
D
t OH
OUT
T3
T3
NOP
D
t OH
OUT
DON’T CARE
UNDEFINED
T4